Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221113918	9730023	0	0
boot_gen_cmd_rd_A	221113918	58935	0	0
boot_ins_cmd_rd_A	221113918	67529	0	0
ctrl_rd_A	221113918	58954	0	0
err_code_test_rd_A	221113918	65900	0	0
intr_enable_rd_A	221113918	64761	0	0
max_num_reqs_between_reseeds_rd_A	221113918	58809	0	0
regwen_rd_A	221113918	66259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	9730023	0	0
T39	737973	26210	0	0
T40	571388	324664	0	0
T41	251471	105211	0	0
T50	1766	0	0	0
T74	0	270070	0	0
T92	2729	0	0	0
T107	0	329193	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	251332	0	0
T221	0	22886	0	0
T222	0	55136	0	0
T223	0	375817	0	0
T224	0	340388	0	0
T225	1705	0	0	0
T226	2497	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	58935	0	0
T39	737973	735	0	0
T40	571388	0	0	0
T41	251471	0	0	0
T50	1766	0	0	0
T92	2729	0	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	7176	0	0
T221	0	691	0	0
T225	1705	0	0	0
T226	2497	0	0	0
T227	0	4323	0	0
T228	0	3044	0	0
T229	0	6695	0	0
T230	0	3445	0	0
T231	0	929	0	0
T232	0	1269	0	0
T233	0	2123	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	67529	0	0
T39	737973	974	0	0
T40	571388	0	0	0
T41	251471	0	0	0
T50	1766	0	0	0
T92	2729	0	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	7975	0	0
T221	0	939	0	0
T225	1705	0	0	0
T226	2497	0	0	0
T227	0	5001	0	0
T228	0	3385	0	0
T229	0	7858	0	0
T230	0	3978	0	0
T231	0	926	0	0
T232	0	1460	0	0
T233	0	2413	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	58954	0	0
T4	23127	5	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	0	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T30	0	4	0	0
T31	2540	0	0	0
T39	0	737	0	0
T49	0	8	0	0
T75	4255	0	0	0
T116	0	1	0	0
T132	0	7	0	0
T220	0	7401	0	0
T221	0	598	0	0
T234	0	7	0	0
T235	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	65900	0	0
T39	737973	943	0	0
T40	571388	0	0	0
T41	251471	0	0	0
T50	1766	0	0	0
T92	2729	0	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	8053	0	0
T221	0	872	0	0
T225	1705	0	0	0
T226	2497	0	0	0
T227	0	4565	0	0
T228	0	3341	0	0
T229	0	7211	0	0
T230	0	3668	0	0
T231	0	1162	0	0
T232	0	1465	0	0
T233	0	2399	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	64761	0	0
T4	23127	207	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	0	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T31	2540	0	0	0
T39	0	1104	0	0
T49	0	34	0	0
T75	4255	0	0	0
T220	0	7508	0	0
T221	0	760	0	0
T227	0	4665	0	0
T228	0	3196	0	0
T235	0	44	0	0
T236	0	35	0	0
T237	0	3	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	58809	0	0
T39	737973	761	0	0
T40	571388	0	0	0
T41	251471	0	0	0
T50	1766	0	0	0
T92	2729	0	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	7026	0	0
T221	0	639	0	0
T225	1705	0	0	0
T226	2497	0	0	0
T227	0	4446	0	0
T228	0	2987	0	0
T229	0	6643	0	0
T230	0	3390	0	0
T231	0	972	0	0
T232	0	1251	0	0
T233	0	2079	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221113918	66259	0	0
T39	737973	793	0	0
T40	571388	0	0	0
T41	251471	0	0	0
T50	1766	0	0	0
T92	2729	0	0	0
T115	1894	0	0	0
T124	1599	0	0	0
T158	1657	0	0	0
T220	0	8111	0	0
T221	0	803	0	0
T225	1705	0	0	0
T226	2497	0	0	0
T227	0	4976	0	0
T228	0	3609	0	0
T229	0	7312	0	0
T230	0	3685	0	0
T231	0	1052	0	0
T232	0	1467	0	0
T233	0	2225	0	0