Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T31,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T3,T29

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T8,T11,T31	Yes	T8,T11,T31	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T24,T32	Yes	T2,T24,T32	INPUT
edn_i[3].edn_req	Yes	Yes	T24,T42,T43	Yes	T24,T42,T43	INPUT
edn_i[4].edn_req	Yes	Yes	T8,T14,T20	Yes	T8,T14,T20	INPUT
edn_i[5].edn_req	Yes	Yes	T8,T9,T24	Yes	T8,T9,T24	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T8,T10	Yes	T3,T8,T10	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T11,T31,T4	Yes	T8,T11,T31	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T11,T31,T4	Yes	T8,T11,T31	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T8,T11,T31	Yes	T8,T11,T31	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T8,T44	Yes	T1,T8,T24	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T24,T32	Yes	T2,T24,T32	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T45,T46,T47	Yes	T2,T24,T32	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T24,T32	Yes	T2,T24,T32	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T24,T42,T43	Yes	T24,T42,T43	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T42,T43,T48	Yes	T24,T42,T43	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T24,T42,T43	Yes	T24,T42,T43	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T8,T14,T42	Yes	T8,T14,T20	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T43,T49,T35	Yes	T43,T49,T35	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T8,T14,T20	Yes	T8,T14,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T8,T9,T24	Yes	T8,T9,T24	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T43,T21,T50	Yes	T9,T28,T43	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T8,T9,T24	Yes	T8,T9,T24	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T8,T10	Yes	T3,T8,T10	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T42,T51,T52	Yes	T8,T42,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T8,T10	Yes	T3,T8,T10	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T8,T9,T11	Yes	T8,T11,T24	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T8,T11,T24	Yes	T2,T8,T11	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T31,T32,T54	Yes	T31,T32,T54	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T22,T23	Yes	T2,T22,T23	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T22,T23	Yes	T2,T22,T23	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T55,T39	Yes	T4,T55,T39	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	226200220	226003283	0	0
CsrngAppIfOut_A	226200220	226003283	0	0
FpvSecCmCntAlertCheck_A	226200220	136	0	0
FpvSecCmGenCmdFifoRptrCheck_A	226200220	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	226200220	90	0	0
FpvSecCmMainFsmCheck_A	226200220	90	0	0
FpvSecCmRegWeOnehotCheck_A	226200220	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	226200220	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	226200220	90	0	0
IntrEdnCmdReqDoneKnownO_A	226200220	226003283	0	0
TlAReadyKnownO_A	226200220	226003283	0	0
TlDValidKnownO_A	226200220	226003283	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	226200220	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[0].EdnDataStable_A	226200220	29839	0	439
gen_edn_if_asserts[0].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[1].EdnDataStable_A	226200220	3227	0	124
gen_edn_if_asserts[1].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[2].EdnDataStable_A	226200220	3353	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[3].EdnDataStable_A	226200220	3099	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[4].EdnDataStable_A	226200220	3667	0	97
gen_edn_if_asserts[4].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[5].EdnDataStable_A	226200220	4590	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	226200220	161886	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	226200220	597723	0	334
gen_edn_if_asserts[6].EdnDataStable_A	226200220	2631	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	226200220	226003283	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	226200220	161886	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	136	0	0
T14	2225	1	0	0
T15	1544	1	0	0
T16	0	1	0	0
T17	0	10	0	0
T20	1968	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T42	3169	0	0	0
T54	2457	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T64	2486	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	90	0	0
T17	24808	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T25	1026	0	0	0
T37	1337	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	1287	0	0	0
T68	2030	0	0	0
T69	14190	0	0	0
T70	1077	0	0	0
T71	1281	0	0	0
T72	1767	0	0	0
T73	1949	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	29839	0	439
T4	18452	3	0	0
T8	1748	3	0	1
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	55	0	1
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T28	844	0	0	0
T30	0	19	0	1
T31	1518	8	0	1
T39	0	66	0	0
T40	0	92	0	0
T42	0	0	0	1
T54	0	4	0	1
T55	0	6	0	1
T62	0	0	0	1
T63	0	0	0	1
T77	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	3227	0	124
T1	860	1	0	0
T2	2638	4	0	0
T3	448	0	0	0
T8	1748	39	0	1
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	3	0	1
T34	0	1	0	0
T42	0	3	0	1
T44	0	0	0	1
T80	0	4	0	1
T81	0	4	0	1
T82	0	4	0	0
T83	0	3	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	3353	0	127
T2	2638	4	0	1
T3	448	0	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T12	0	3	0	1
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	12	0	1
T31	1518	0	0	0
T32	0	4	0	1
T43	0	3	0	1
T49	0	3	0	1
T50	0	3	0	1
T83	0	3	0	1
T87	0	3	0	1
T88	0	4	0	0
T89	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	3099	0	107
T4	18452	0	0	0
T12	0	15	0	1
T14	2225	0	0	0
T24	1235	3	0	1
T28	844	0	0	0
T29	879	0	0	0
T30	3237	0	0	0
T31	1518	0	0	0
T32	2032	0	0	0
T42	0	30	0	1
T43	0	16	0	1
T48	0	4	0	0
T49	0	3	0	1
T50	0	0	0	1
T55	18130	0	0	0
T77	2312	0	0	0
T83	0	63	0	1
T90	0	3	0	1
T91	0	4	0	0
T92	0	3	0	1
T93	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	3667	0	97
T4	18452	0	0	0
T8	1748	3	0	1
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T12	0	0	0	1
T14	0	1	0	0
T20	0	4	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T28	844	0	0	0
T31	1518	0	0	0
T35	0	1	0	0
T42	0	25	0	1
T43	0	39	0	1
T49	0	12	0	1
T64	0	4	0	1
T83	0	0	0	1
T94	0	4	0	0
T95	0	4	0	1
T96	0	0	0	1
T97	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	4590	0	96
T4	18452	0	0	0
T8	1748	3	0	1
T9	2893	4	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T12	0	3	0	1
T21	0	159	0	1
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	3	0	1
T28	844	3	0	1
T31	1518	0	0	0
T43	0	33	0	1
T50	0	51	0	1
T84	0	3	0	1
T98	0	3	0	1
T99	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	597723	0	334
T1	860	318	0	0
T2	2638	477	0	0
T3	448	97	0	0
T8	1748	280	0	0
T9	2893	1578	0	2
T10	2009	660	0	2
T11	3416	79	0	0
T20	0	0	0	2
T22	1595	1533	0	2
T23	1262	1184	0	2
T24	1235	11	0	0
T39	0	0	0	2
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	2631	0	84
T3	448	1	0	0
T8	1748	3	0	1
T9	2893	0	0	0
T10	2009	4	0	0
T11	3416	0	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T28	844	0	0	0
T31	1518	0	0	0
T42	0	43	0	1
T43	0	3	0	1
T50	0	0	0	1
T53	0	4	0	1
T74	0	1	0	0
T82	0	4	0	1
T83	0	0	0	1
T84	0	0	0	1
T100	0	3	0	1
T101	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	161886	0	0
T1	860	37	0	0
T2	2638	0	0	0
T3	448	7	0	0
T8	1748	0	0	0
T9	2893	0	0	0
T10	2009	0	0	0
T11	3416	0	0	0
T14	0	1141	0	0
T15	0	255	0	0
T16	0	1139	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	450	0	0
T34	0	7	0	0
T35	0	17	0	0
T78	0	401	0	0
T79	0	1112	0	0