Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	226698821	10372654	0	0
boot_gen_cmd_rd_A	226698821	41818	0	0
boot_ins_cmd_rd_A	226698821	48252	0	0
ctrl_rd_A	226698821	42288	0	0
err_code_test_rd_A	226698821	48890	0	0
intr_enable_rd_A	226698821	46447	0	0
max_num_reqs_between_reseeds_rd_A	226698821	42078	0	0
regwen_rd_A	226698821	48974	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	10372654	0	0
T15	1544	0	0	0
T34	1872	0	0	0
T39	415150	170238	0	0
T40	478163	278576	0	0
T41	0	191586	0	0
T42	3169	0	0	0
T54	2457	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T64	2486	0	0	0
T115	20502	0	0	0
T119	0	49982	0	0
T228	0	28506	0	0
T229	0	260337	0	0
T230	0	101423	0	0
T231	0	64454	0	0
T232	0	51905	0	0
T233	0	388409	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	41818	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	0	0	0
T228	731040	395	0	0
T229	636639	0	0	0
T230	277540	1613	0	0
T233	0	5952	0	0
T234	0	7275	0	0
T235	0	3752	0	0
T236	0	2869	0	0
T237	0	4488	0	0
T238	0	2371	0	0
T239	0	1519	0	0
T240	0	6162	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	48252	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	0	0	0
T228	731040	362	0	0
T229	636639	0	0	0
T230	277540	1814	0	0
T233	0	6854	0	0
T234	0	8489	0	0
T235	0	4327	0	0
T236	0	3256	0	0
T237	0	5340	0	0
T238	0	2763	0	0
T239	0	1689	0	0
T240	0	7179	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	42288	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	6	0	0
T228	731040	463	0	0
T229	636639	0	0	0
T230	277540	1641	0	0
T233	0	5878	0	0
T234	0	7399	0	0
T235	0	3650	0	0
T236	0	2875	0	0
T237	0	4419	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0
T244	0	19	0	0
T245	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	48890	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	0	0	0
T228	731040	427	0	0
T229	636639	0	0	0
T230	277540	2007	0	0
T233	0	6782	0	0
T234	0	7904	0	0
T235	0	4460	0	0
T236	0	3666	0	0
T237	0	5326	0	0
T238	0	2699	0	0
T239	0	1879	0	0
T240	0	7583	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	46447	0	0
T35	1220	0	0	0
T79	1815	0	0	0
T95	2495	0	0	0
T96	1060	0	0	0
T100	1015	0	0	0
T114	2637	0	0	0
T118	8543	24	0	0
T137	2711	0	0	0
T203	3910	0	0	0
T228	0	469	0	0
T230	0	1804	0	0
T233	0	6128	0	0
T234	0	7267	0	0
T244	0	100	0	0
T246	0	37	0	0
T247	0	35	0	0
T248	0	45	0	0
T249	0	107	0	0
T250	2338	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	42078	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	0	0	0
T228	731040	395	0	0
T229	636639	0	0	0
T230	277540	1636	0	0
T233	0	6257	0	0
T234	0	6729	0	0
T235	0	3764	0	0
T236	0	2782	0	0
T237	0	4760	0	0
T238	0	2335	0	0
T239	0	1477	0	0
T240	0	5958	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226698821	48974	0	0
T52	797	0	0	0
T83	1932	0	0	0
T88	1602	0	0	0
T121	2627	0	0	0
T228	731040	453	0	0
T229	636639	0	0	0
T230	277540	1764	0	0
T233	0	6563	0	0
T234	0	8195	0	0
T235	0	4011	0	0
T236	0	3257	0	0
T237	0	5156	0	0
T238	0	3109	0	0
T239	0	1922	0	0
T240	0	7315	0	0
T241	1215	0	0	0
T242	1102	0	0	0
T243	2204	0	0	0