Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	658161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5360912

1

T1

28

T2

45

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1585610	1			T1	37		T2	32		T3	77
values[0x0]	2049739	1			T1	12		T2	21		T3	19
values[0x1]	2383724	1			T1	12		T2	30		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325255	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5693818

1

T1

38

T2

56

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22670	1			T5	9		T24	457		T34	58
valid_sources[0x01]	24588	1			T5	7		T24	412		T34	258
valid_sources[0x02]	24709	1			T5	7		T24	437		T25	2
valid_sources[0x03]	24148	1			T1	1		T5	11		T24	439
valid_sources[0x04]	24210	1			T5	6		T24	484		T11	6
valid_sources[0x05]	22877	1			T5	8		T24	463		T34	202
valid_sources[0x06]	23192	1			T5	10		T24	460		T34	223
valid_sources[0x07]	27329	1			T5	1		T24	457		T25	1
valid_sources[0x08]	24134	1			T5	7		T24	505		T34	198
valid_sources[0x09]	22003	1			T5	2		T24	491		T34	297
valid_sources[0x0a]	23686	1			T5	3		T24	474		T34	127
valid_sources[0x0b]	22323	1			T5	2		T24	499		T34	1277
valid_sources[0x0c]	24279	1			T5	7		T24	466		T34	594
valid_sources[0x0d]	24686	1			T5	2		T24	517		T25	1
valid_sources[0x0e]	24867	1			T5	2		T24	538		T25	2
valid_sources[0x0f]	23197	1			T2	1		T5	2		T10	1
valid_sources[0x10]	23013	1			T5	5		T24	492		T34	592
valid_sources[0x11]	23324	1			T5	6		T24	441		T34	111
valid_sources[0x12]	24620	1			T5	3		T24	471		T34	254
valid_sources[0x13]	22222	1			T5	12		T10	1		T24	513
valid_sources[0x14]	23602	1			T5	6		T24	464		T34	610
valid_sources[0x15]	24314	1			T5	5		T10	1		T24	502
valid_sources[0x16]	22451	1			T5	4		T24	451		T34	234
valid_sources[0x17]	22565	1			T5	8		T24	498		T34	59
valid_sources[0x18]	22271	1			T3	110		T5	7		T10	1
valid_sources[0x19]	23730	1			T5	6		T10	1		T24	461
valid_sources[0x1a]	22711	1			T5	7		T10	1		T24	524
valid_sources[0x1b]	23875	1			T5	13		T10	1		T24	484
valid_sources[0x1c]	24668	1			T5	14		T24	468		T25	1
valid_sources[0x1d]	23920	1			T5	6		T10	3		T24	427
valid_sources[0x1e]	23683	1			T5	5		T24	464		T34	316
valid_sources[0x1f]	25491	1			T5	2		T24	479		T34	832
valid_sources[0x20]	23264	1			T5	7		T10	1		T24	514
valid_sources[0x21]	22529	1			T5	2		T24	519		T34	209
valid_sources[0x22]	23583	1			T5	6		T10	1		T24	482
valid_sources[0x23]	23668	1			T5	2		T24	445		T11	12
valid_sources[0x24]	23530	1			T5	3		T24	500		T34	322
valid_sources[0x25]	23199	1			T5	3		T24	459		T34	510
valid_sources[0x26]	23643	1			T5	5		T24	465		T34	606
valid_sources[0x27]	24248	1			T5	3		T24	400		T34	203
valid_sources[0x28]	24817	1			T5	4		T24	446		T38	5
valid_sources[0x29]	22410	1			T5	3		T24	481		T34	368
valid_sources[0x2a]	25067	1			T5	8		T24	442		T38	2
valid_sources[0x2b]	22799	1			T24	455		T34	369		T37	1
valid_sources[0x2c]	24571	1			T5	2		T10	1		T24	490
valid_sources[0x2d]	24078	1			T5	6		T10	4		T24	445
valid_sources[0x2e]	25031	1			T5	2		T24	510		T34	318
valid_sources[0x2f]	21965	1			T5	2		T24	462		T34	388
valid_sources[0x30]	23506	1			T5	6		T10	1		T24	471
valid_sources[0x31]	24019	1			T5	8		T24	444		T11	3
valid_sources[0x32]	24837	1			T5	1		T10	2		T24	493
valid_sources[0x33]	24360	1			T5	7		T24	518		T34	156
valid_sources[0x34]	24807	1			T5	4		T24	502		T34	101
valid_sources[0x35]	23666	1			T5	14		T24	487		T34	508
valid_sources[0x36]	22465	1			T5	2		T24	465		T34	404
valid_sources[0x37]	26611	1			T4	17		T5	6		T24	445
valid_sources[0x38]	22749	1			T5	11		T10	1		T24	444
valid_sources[0x39]	23069	1			T5	2		T24	456		T34	271
valid_sources[0x3a]	23467	1			T5	1		T24	453		T34	486
valid_sources[0x3b]	25002	1			T5	7		T24	478		T34	237
valid_sources[0x3c]	23485	1			T5	8		T24	465		T34	566
valid_sources[0x3d]	23650	1			T5	11		T10	2		T24	469
valid_sources[0x3e]	22251	1			T5	8		T24	497		T25	1
valid_sources[0x3f]	23231	1			T10	1		T24	471		T34	406
valid_sources[0x40]	23948	1			T5	2		T10	4		T24	454
valid_sources[0x41]	22419	1			T2	2		T5	17		T24	484
valid_sources[0x42]	24244	1			T5	5		T24	453		T34	911
valid_sources[0x43]	24110	1			T5	5		T24	451		T25	5
valid_sources[0x44]	23109	1			T5	6		T24	488		T11	2
valid_sources[0x45]	23963	1			T5	10		T10	1		T24	509
valid_sources[0x46]	24646	1			T5	4		T24	483		T34	443
valid_sources[0x47]	22912	1			T5	2		T24	493		T25	5
valid_sources[0x48]	21442	1			T5	5		T24	521		T34	296
valid_sources[0x49]	24176	1			T5	7		T24	476		T34	91
valid_sources[0x4a]	24794	1			T2	1		T5	4		T10	1
valid_sources[0x4b]	23032	1			T5	2		T24	478		T34	361
valid_sources[0x4c]	21265	1			T5	1		T24	532		T34	343
valid_sources[0x4d]	24596	1			T5	14		T10	3		T24	434
valid_sources[0x4e]	22279	1			T5	6		T10	1		T24	447
valid_sources[0x4f]	22469	1			T5	9		T24	473		T34	209
valid_sources[0x50]	23651	1			T5	9		T24	480		T34	787
valid_sources[0x51]	21175	1			T5	4		T24	454		T25	2
valid_sources[0x52]	23560	1			T5	6		T24	469		T25	2
valid_sources[0x53]	24149	1			T24	491		T25	1		T11	6
valid_sources[0x54]	22009	1			T5	1		T24	513		T38	5
valid_sources[0x55]	24939	1			T5	6		T24	445		T34	1367
valid_sources[0x56]	23241	1			T5	13		T24	546		T34	279
valid_sources[0x57]	23071	1			T5	6		T10	1		T24	528
valid_sources[0x58]	23296	1			T5	7		T24	517		T34	337
valid_sources[0x59]	23458	1			T5	3		T24	448		T34	465
valid_sources[0x5a]	24626	1			T5	11		T10	1		T24	459
valid_sources[0x5b]	23003	1			T1	1		T5	3		T24	465
valid_sources[0x5c]	22906	1			T5	8		T24	493		T34	414
valid_sources[0x5d]	22599	1			T5	4		T24	524		T25	2
valid_sources[0x5e]	24160	1			T5	5		T24	527		T38	2
valid_sources[0x5f]	21559	1			T5	1		T24	467		T34	162
valid_sources[0x60]	24471	1			T5	4		T24	431		T25	1
valid_sources[0x61]	23427	1			T5	12		T24	446		T25	1
valid_sources[0x62]	23202	1			T5	8		T24	485		T34	390
valid_sources[0x63]	24099	1			T5	4		T10	4		T24	431
valid_sources[0x64]	23029	1			T5	3		T24	463		T11	1
valid_sources[0x65]	24313	1			T5	3		T24	485		T25	1
valid_sources[0x66]	24601	1			T5	3		T24	505		T34	259
valid_sources[0x67]	21999	1			T5	3		T24	445		T34	158
valid_sources[0x68]	23221	1			T5	9		T24	495		T34	101
valid_sources[0x69]	22259	1			T5	5		T24	479		T34	608
valid_sources[0x6a]	25355	1			T5	13		T24	451		T34	443
valid_sources[0x6b]	24783	1			T5	4		T24	463		T25	1
valid_sources[0x6c]	22577	1			T5	4		T24	465		T11	5
valid_sources[0x6d]	22531	1			T5	8		T6	70		T24	487
valid_sources[0x6e]	23641	1			T5	7		T24	401		T34	679
valid_sources[0x6f]	22327	1			T5	6		T24	418		T34	329
valid_sources[0x70]	22846	1			T5	13		T24	492		T34	510
valid_sources[0x71]	24238	1			T5	8		T24	472		T34	372
valid_sources[0x72]	22293	1			T5	2		T24	495		T34	536
valid_sources[0x73]	23288	1			T5	6		T10	1		T24	442
valid_sources[0x74]	23001	1			T5	4		T24	458		T34	714
valid_sources[0x75]	22438	1			T5	9		T24	499		T34	76
valid_sources[0x76]	22896	1			T5	19		T24	468		T34	415
valid_sources[0x77]	22554	1			T5	3		T24	491		T34	105
valid_sources[0x78]	23510	1			T5	13		T24	451		T34	249
valid_sources[0x79]	24812	1			T5	4		T10	1		T24	412
valid_sources[0x7a]	23229	1			T5	5		T24	463		T34	674
valid_sources[0x7b]	23815	1			T5	12		T24	505		T25	1
valid_sources[0x7c]	24813	1			T10	2		T24	514		T34	482
valid_sources[0x7d]	22347	1			T5	2		T24	425		T34	390
valid_sources[0x7e]	22875	1			T5	8		T24	452		T34	443
valid_sources[0x7f]	23844	1			T5	5		T24	473		T34	256
valid_sources[0x80]	25114	1			T5	6		T24	448		T34	1023

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1350340

1

T1

13

T2

7

T3

3

values[0x0]

all_enables

biggest_size

2006054

1

T1

7

T2

18

T3

17

values[0x1]

all_enables

biggest_size

2004518

1

T1

8

T2

20

T3

12