Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2797	1			T3	2		T5	10		T24	11
non_zero_bins[1]	2015	1			T3	1		T5	11		T24	16
zero	9631	1			T1	5		T2	6		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	562	1			T5	3		T24	5		T38	1
uni	3845	1			T3	2		T5	16		T24	26
gen	4584	1			T1	3		T2	3		T3	1
res	856	1			T2	1		T5	4		T24	4
ins	4596	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9525

1

T1

1

T2

3

T3

5

mubi_true

4918

1

T1

4

T2

3

T4

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T2

1

T291

1

T292

1

pass

14427

1

T1

5

T2

5

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	131	1			T24	1		T34	2		T115	1
upd	non_zero_bins[0]	pass	mubi_true	113	1			T5	1		T24	1		T34	2
upd	non_zero_bins[1]	pass	mubi_false	112	1			T24	3		T34	1		T35	3
upd	non_zero_bins[1]	pass	mubi_true	93	1			T5	2		T34	2		T35	1
upd	zero	pass	mubi_false	56	1			T35	1		T72	1		T74	2
upd	zero	pass	mubi_true	57	1			T38	1		T36	1		T46	1
uni	zero	pass	mubi_false	2849	1			T3	2		T5	12		T24	21
uni	zero	pass	mubi_true	996	1			T5	4		T24	5		T34	14
gen	non_zero_bins[0]	pass	mubi_false	474	1			T5	1		T11	3		T34	4
gen	non_zero_bins[0]	pass	mubi_true	564	1			T5	1		T24	1		T34	6
gen	non_zero_bins[1]	pass	mubi_false	383	1			T3	1		T5	4		T24	3
gen	non_zero_bins[1]	pass	mubi_true	395	1			T5	2		T24	5		T11	1
gen	zero	fail	mubi_false	12	1			T291	1		T293	1		T294	1
gen	zero	pass	mubi_false	2010	1			T1	1		T2	1		T5	7
gen	zero	pass	mubi_true	746	1			T1	2		T2	2		T4	1
res	non_zero_bins[0]	pass	mubi_false	197	1			T5	2		T34	1		T35	4
res	non_zero_bins[0]	pass	mubi_true	206	1			T24	2		T34	3		T15	3
res	non_zero_bins[1]	pass	mubi_false	150	1			T5	1		T35	1		T41	1
res	non_zero_bins[1]	pass	mubi_true	114	1			T24	1		T11	2		T115	2
res	zero	fail	mubi_false	4	1			T2	1		T292	1		T295	1
res	zero	pass	mubi_false	100	1			T24	1		T34	1		T35	2
res	zero	pass	mubi_true	85	1			T5	1		T115	1		T84	1
ins	non_zero_bins[0]	pass	mubi_false	528	1			T3	2		T5	1		T24	2
ins	non_zero_bins[0]	pass	mubi_true	584	1			T5	4		T24	4		T34	7
ins	non_zero_bins[1]	pass	mubi_false	420	1			T5	1		T24	4		T11	1
ins	non_zero_bins[1]	pass	mubi_true	348	1			T5	1		T34	3		T95	2
ins	zero	pass	mubi_false	2099	1			T2	1		T4	2		T5	9
ins	zero	pass	mubi_true	617	1			T1	2		T2	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded