Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for csrng_glen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
2762 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T5 |
7 |
glens[1] |
37 |
1 |
|
|
T38 |
1 |
|
T107 |
1 |
|
T23 |
1 |
glens[2] |
37 |
1 |
|
|
T3 |
1 |
|
T46 |
1 |
|
T84 |
1 |
glens[3] |
37 |
1 |
|
|
T93 |
1 |
|
T296 |
1 |
|
T297 |
1 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
12 |
1 |
|
|
T291 |
1 |
|
T293 |
1 |
|
T294 |
1 |
pass |
4572 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for csrng_genbits_cross
Uncovered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | NUMBER | STATUS |
[glens[1] , glens[2] , glens[3]] |
[fail] |
-- |
-- |
3 |
|
Covered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
12 |
1 |
|
|
T291 |
1 |
|
T293 |
1 |
|
T294 |
1 |
glens[0] |
pass |
2750 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T5 |
7 |
glens[1] |
pass |
37 |
1 |
|
|
T38 |
1 |
|
T107 |
1 |
|
T23 |
1 |
glens[2] |
pass |
37 |
1 |
|
|
T3 |
1 |
|
T46 |
1 |
|
T84 |
1 |
glens[3] |
pass |
37 |
1 |
|
|
T93 |
1 |
|
T296 |
1 |
|
T297 |
1 |