Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T91
1	1	Covered	T1,T4,T25

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T15
1	1	Covered	T2,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T4,T7,T8

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T4,T7,T8

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T7,T8

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T11,T15
AutoCaptGenCnt	143	Covered	T2,T11,T7
AutoCaptReseedCnt	141	Covered	T2,T11,T15
AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns	69	Covered	T2,T10,T11
AutoSendGenCmd	150	Covered	T2,T11,T7
AutoSendReseedCmd	162	Covered	T2,T11,T15
BootDone	98	Covered	T1,T25,T78
BootGenAckWait	90	Covered	T1,T4,T25
BootInsAckWait	80	Covered	T1,T4,T25
BootLoadGen	85	Covered	T1,T4,T25
BootLoadIns	65	Covered	T1,T4,T25
BootLoadUni	102	Covered	T1,T25,T78
BootPulse	94	Covered	T1,T25,T78
BootUniAckWait	107	Covered	T1,T25,T78
Error	188	Covered	T4,T7,T8
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T2,T10
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T11,T15
AutoAckWait->Error	188	Covered	T126,T127,T128
AutoAckWait->Idle	211	Covered	T15,T21,T22
AutoAckWait->RejectCsrngEntropy	188	Covered	T129,T66,T130
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T11,T7
AutoCaptGenCnt->Error	188	Covered	T131,T132,T133
AutoCaptGenCnt->Idle	211	Covered	T134,T135,T136
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T137,T138,T139
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T11,T15
AutoCaptReseedCnt->Error	188	Covered	T140,T141,T142
AutoCaptReseedCnt->Idle	211	Covered	T143,T70,T144
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T52,T69,T145
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T11,T7
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T11,T15
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T11,T107,T12
AutoDispatch->RejectCsrngEntropy	188	Covered	T10,T94,T146
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait->Error	188	Covered	T147,T148,T149
AutoFirstAckWait->Idle	211	Covered	T15,T150,T151
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T152,T153,T154
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns->Error	188	Covered	T155,T156,T157
AutoLoadIns->Idle	211	Covered	T10,T7,T90
AutoLoadIns->RejectCsrngEntropy	188	Covered	T78,T158,T159
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T11,T15
AutoSendGenCmd->Error	188	Covered	T7,T160,T161
AutoSendGenCmd->Idle	211	Covered	T162,T163,T164
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T165,T166,T167
AutoSendReseedCmd->AutoAckWait	168	Covered	T11,T15,T107
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T168,T169
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T2,T121,T122
BootDone->BootLoadUni	102	Covered	T1,T25,T78
BootDone->Error	188	Covered	T82,T58,T170
BootDone->Idle	211	Covered	T80,T50,T171
BootDone->RejectCsrngEntropy	188	Covered	T172,T102,T173
BootGenAckWait->BootPulse	94	Covered	T1,T25,T78
BootGenAckWait->Error	188	Covered	T174,T175
BootGenAckWait->Idle	211	Covered	T92,T57,T176
BootGenAckWait->RejectCsrngEntropy	188	Covered	T63,T86,T120
BootInsAckWait->BootLoadGen	85	Covered	T1,T4,T25
BootInsAckWait->Error	188	Covered	T177,T57,T178
BootInsAckWait->Idle	211	Covered	T4,T91,T82
BootInsAckWait->RejectCsrngEntropy	188	Covered	T90,T106,T179
BootLoadGen->BootGenAckWait	90	Covered	T1,T4,T25
BootLoadGen->Error	188	Covered	T180,T181,T182
BootLoadGen->Idle	211	Covered	T101,T183,T184
BootLoadGen->RejectCsrngEntropy	188	Covered	T185,T186,T187
BootLoadIns->BootInsAckWait	80	Covered	T1,T4,T25
BootLoadIns->Error	188	Covered	T4,T188,T189
BootLoadIns->Idle	211	Covered	T190,T191,T192
BootLoadIns->RejectCsrngEntropy	188	Covered	T39,T193,T194
BootLoadUni->BootUniAckWait	107	Covered	T1,T25,T78
BootLoadUni->Error	188	Covered	T16,T54,T195
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T196,T197,T198
BootPulse->BootDone	98	Covered	T1,T25,T78
BootPulse->Error	188	Covered	T199,T200
BootPulse->Idle	211	Covered	T201,T202,T203
BootPulse->RejectCsrngEntropy	188	Covered	T89,T104,T204
BootUniAckWait->Error	188	Covered	T205,T206
BootUniAckWait->Idle	112	Covered	T25,T78,T46
BootUniAckWait->RejectCsrngEntropy	188	Covered	T1,T25,T51
Idle->AutoLoadIns	69	Covered	T2,T10,T11
Idle->BootLoadIns	65	Covered	T1,T4,T25
Idle->Error	188	Covered	T17,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T1,T10,T106
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T73,T207,T208
RejectCsrngEntropy->Idle	211	Covered	T1,T2,T10
SWPortMode->Error	188	Covered	T88,T59,T209
SWPortMode->Idle	211	Covered	T1,T2,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T25,T78

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T78
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T25
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T78
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T25,T78
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T25,T78,T91
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T78
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T25,T78
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T25,T78
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T11,T107,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T11,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T11,T7,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T15,T107
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T80,T81

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T7,T8
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T2,T10
0	-	-	1	Covered	T1,T2,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	220552487	144030	0	0
FpvSecCmErrorStEscalate_A	220552487	145070	0	0
u_state_regs_A	220513937	220332678	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	144030	0	0
T4	508	243	0	0
T5	26607	0	0	0
T6	2027	0	0	0
T7	0	1137	0	0
T8	0	332	0	0
T9	0	585	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T16	0	1112	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	497	0	0
T81	0	599	0	0
T82	0	410	0	0
T85	0	365	0	0
T88	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	145070	0	0
T4	508	244	0	0
T5	26607	0	0	0
T6	2027	0	0	0
T7	0	1138	0	0
T8	0	333	0	0
T9	0	586	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T16	0	1113	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	498	0	0
T81	0	600	0	0
T82	0	411	0	0
T85	0	366	0	0
T88	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220513937	220332678	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	335	222	0	0
T5	26607	25887	0	0
T6	2013	1874	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0