Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T105
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T29,T33
1	0	1	Covered	T2,T4,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T7

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	440356370	1054979	0	0
DepthKnown_A	441104974	440742456	0	0
RvalidKnown_A	441104974	440742456	0	0
WreadyKnown_A	441104974	440742456	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	440725662	1138120	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440356370	1054979	0	0
T2	5880	684	0	0
T3	8776	0	0	0
T4	160	0	0	0
T5	53214	0	0	0
T6	820	0	0	0
T7	0	168	0	0
T8	0	169	0	0
T10	5180	857	0	0
T11	7460	2763	0	0
T15	0	2412	0	0
T24	676078	0	0	0
T25	4168	0	0	0
T38	2966	0	0	0
T78	0	405	0	0
T90	0	394	0	0
T106	0	233	0	0
T107	0	8253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441104974	440742456	0	0
T1	4404	4220	0	0
T2	5880	5724	0	0
T3	8776	8648	0	0
T4	1016	790	0	0
T5	53214	51774	0	0
T6	4054	3776	0	0
T10	5180	4986	0	0
T11	7460	7348	0	0
T24	676078	676060	0	0
T25	4168	4004	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441104974	440742456	0	0
T1	4404	4220	0	0
T2	5880	5724	0	0
T3	8776	8648	0	0
T4	1016	790	0	0
T5	53214	51774	0	0
T6	4054	3776	0	0
T10	5180	4986	0	0
T11	7460	7348	0	0
T24	676078	676060	0	0
T25	4168	4004	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441104974	440742456	0	0
T1	4404	4220	0	0
T2	5880	5724	0	0
T3	8776	8648	0	0
T4	1016	790	0	0
T5	53214	51774	0	0
T6	4054	3776	0	0
T10	5180	4986	0	0
T11	7460	7348	0	0
T24	676078	676060	0	0
T25	4168	4004	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	440725662	1138120	0	0
T2	5880	684	0	0
T3	8776	0	0	0
T4	1016	278	0	0
T5	53214	0	0	0
T6	4054	0	0	0
T7	0	1912	0	0
T10	5180	857	0	0
T11	7460	2763	0	0
T15	0	2412	0	0
T24	676078	0	0	0
T25	4168	0	0	0
T30	0	7	0	0
T38	2966	0	0	0
T78	0	405	0	0
T90	0	394	0	0
T106	0	233	0	0
T107	0	4116	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T108,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T29,T33
1	0	1	Covered	T2,T4,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220178185	520901	0	0
DepthKnown_A	220552487	220371228	0	0
RvalidKnown_A	220552487	220371228	0	0
WreadyKnown_A	220552487	220371228	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220362831	562510	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220178185	520901	0	0
T2	2940	252	0	0
T3	4388	0	0	0
T4	80	0	0	0
T5	26607	0	0	0
T6	410	0	0	0
T7	0	43	0	0
T8	0	40	0	0
T10	2590	383	0	0
T11	3730	1380	0	0
T15	0	1196	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T38	1483	0	0	0
T78	0	209	0	0
T90	0	160	0	0
T106	0	82	0	0
T107	0	4116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220362831	562510	0	0
T2	2940	252	0	0
T3	4388	0	0	0
T4	508	140	0	0
T5	26607	0	0	0
T6	2027	0	0	0
T7	0	933	0	0
T10	2590	383	0	0
T11	3730	1380	0	0
T15	0	1196	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T38	1483	0	0	0
T78	0	209	0	0
T90	0	160	0	0
T106	0	82	0	0
T107	0	4116	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T105
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T109,T110,T111
1	0	1	Covered	T2,T4,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220178185	534078	0	0
DepthKnown_A	220552487	220371228	0	0
RvalidKnown_A	220552487	220371228	0	0
WreadyKnown_A	220552487	220371228	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220362831	575610	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220178185	534078	0	0
T2	2940	432	0	0
T3	4388	0	0	0
T4	80	0	0	0
T5	26607	0	0	0
T6	410	0	0	0
T7	0	125	0	0
T8	0	129	0	0
T10	2590	474	0	0
T11	3730	1383	0	0
T15	0	1216	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T38	1483	0	0	0
T78	0	196	0	0
T90	0	234	0	0
T106	0	151	0	0
T107	0	4137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220362831	575610	0	0
T2	2940	432	0	0
T3	4388	0	0	0
T4	508	138	0	0
T5	26607	0	0	0
T6	2027	0	0	0
T7	0	979	0	0
T10	2590	474	0	0
T11	3730	1383	0	0
T15	0	1216	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T30	0	7	0	0
T38	1483	0	0	0
T78	0	196	0	0
T90	0	234	0	0
T106	0	151	0	0