Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
SCORELINE
95.24 100.00
tb.dut.u_edn_core.u_prim_packer_fifo_cs

Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1


Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
SCORECOND
95.24 95.24
tb.dut.u_edn_core.u_prim_packer_fifo_cs

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T21,T22
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T25
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 1764419896 197080637 0 7712
ValidOPairedWithReadyI_A 1764419896 197080637 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1764419896 197080637 0 7712
T1 4404 1395 0 2
T2 5880 1737 0 2
T3 8776 2149 0 2
T4 1016 0 0 2
T5 53214 11931 0 2
T6 4054 1015 0 2
T7 4832 1130 0 2
T10 5180 1192 0 2
T11 11190 1120 0 3
T15 0 742 0 0
T22 0 984 0 0
T24 676078 337137 0 2
T25 4168 1285 0 2
T29 6186 1031 0 3
T34 632590 315207 0 2
T36 3330 924 0 2
T37 7146 0 0 3
T38 2966 0 0 2
T40 0 3485 0 0
T42 0 1598 0 0
T44 0 2316 0 0
T53 1932 0 0 2
T75 1834 0 0 1
T78 5670 0 0 3
T79 4173 0 0 3
T83 0 1055 0 0
T84 0 1280 0 0
T85 0 426 0 0
T93 7902 0 0 2

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1764419896 197080637 0 0
T1 4404 1395 0 0
T2 5880 1737 0 0
T3 8776 2149 0 0
T4 1016 0 0 0
T5 53214 11931 0 0
T6 4054 1015 0 0
T7 4832 1130 0 0
T10 5180 1192 0 0
T11 11190 1120 0 0
T15 0 742 0 0
T22 0 984 0 0
T24 676078 337137 0 0
T25 4168 1285 0 0
T29 6186 1031 0 0
T34 632590 315207 0 0
T36 3330 924 0 0
T37 7146 0 0 0
T38 2966 0 0 0
T40 0 3485 0 0
T42 0 1598 0 0
T44 0 2316 0 0
T53 1932 0 0 0
T75 1834 0 0 0
T78 5670 0 0 0
T79 4173 0 0 0
T83 0 1055 0 0
T84 0 1280 0 0
T85 0 426 0 0
T93 7902 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T21,T22
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
Branches 14 12 85.71
TERNARY 142 4 3 75.00
TERNARY 147 3 2 66.67
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 126638 0 964
ValidOPairedWithReadyI_A 220552487 126638 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 126638 0 964
T1 2202 191 0 1
T2 2940 87 0 1
T3 4388 50 0 1
T4 508 0 0 1
T5 26607 0 0 1
T6 2027 42 0 1
T10 2590 68 0 1
T11 3730 0 0 1
T24 338039 0 0 1
T25 2084 116 0 1
T29 0 68 0 0
T37 0 3 0 0
T38 0 12 0 0
T78 0 138 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 126638 0 0
T1 2202 191 0 0
T2 2940 87 0 0
T3 4388 50 0 0
T4 508 0 0 0
T5 26607 0 0 0
T6 2027 42 0 0
T10 2590 68 0 0
T11 3730 0 0 0
T24 338039 0 0 0
T25 2084 116 0 0
T29 0 68 0 0
T37 0 3 0 0
T38 0 12 0 0
T78 0 138 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T25,T52
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 195577742 0 964
ValidOPairedWithReadyI_A 220552487 195577742 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 195577742 0 964
T1 2202 1278 0 1
T2 2940 1737 0 1
T3 4388 2149 0 1
T4 508 0 0 1
T5 26607 11931 0 1
T6 2027 1015 0 1
T7 0 1130 0 0
T10 2590 1192 0 1
T11 3730 0 0 1
T24 338039 337137 0 1
T25 2084 1285 0 1
T34 0 315207 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 195577742 0 0
T1 2202 1278 0 0
T2 2940 1737 0 0
T3 4388 2149 0 0
T4 508 0 0 0
T5 26607 11931 0 0
T6 2027 1015 0 0
T7 0 1130 0 0
T10 2590 1192 0 0
T11 3730 0 0 0
T24 338039 337137 0 0
T25 2084 1285 0 0
T34 0 315207 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT11,T15,T42

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT11,T15,T42
10CoveredT11,T29,T15
11CoveredT11,T15,T42

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T15,T42

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT11,T29,T15

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT11,T29,T15
11CoveredT11,T29,T15

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T29,T15

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T29,T15

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T29,T15

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T29,T15

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT11,T29,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT121,T66,T196
11CoveredT11,T29,T15

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT11,T29,T15
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T11,T29,T15
0 0 1 Covered T11,T29,T15
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T29,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T29,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 266403 0 964
ValidOPairedWithReadyI_A 220552487 266403 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 266403 0 964
T7 2416 0 0 1
T11 3730 1120 0 1
T15 0 742 0 0
T22 0 984 0 0
T29 2062 1031 0 1
T34 316295 0 0 1
T36 1665 0 0 1
T37 2382 0 0 1
T38 1483 0 0 1
T40 0 1460 0 0
T42 0 1598 0 0
T44 0 1364 0 0
T53 966 0 0 1
T78 1890 0 0 1
T79 1391 0 0 1
T83 0 1055 0 0
T84 0 1280 0 0
T85 0 426 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 266403 0 0
T7 2416 0 0 0
T11 3730 1120 0 0
T15 0 742 0 0
T22 0 984 0 0
T29 2062 1031 0 0
T34 316295 0 0 0
T36 1665 0 0 0
T37 2382 0 0 0
T38 1483 0 0 0
T40 0 1460 0 0
T42 0 1598 0 0
T44 0 1364 0 0
T53 966 0 0 0
T78 1890 0 0 0
T79 1391 0 0 0
T83 0 1055 0 0
T84 0 1280 0 0
T85 0 426 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T36,T37

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T36,T37
10CoveredT1,T36,T37
11CoveredT1,T36,T37

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T36,T37

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T36,T37

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T36,T37
11CoveredT1,T36,T37

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T36,T37

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T36,T37

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T36,T37

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T36,T37

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T36,T37
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T89,T171
11CoveredT1,T36,T37

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T36,T37
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T36,T37
0 0 1 Covered T1,T36,T37
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T36,T37
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T36,T37
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 262473 0 964
ValidOPairedWithReadyI_A 220552487 262473 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 262473 0 964
T1 2202 117 0 1
T2 2940 0 0 1
T3 4388 0 0 1
T4 508 0 0 1
T5 26607 0 0 1
T6 2027 0 0 1
T10 2590 0 0 1
T11 3730 0 0 1
T12 0 1706 0 0
T24 338039 0 0 1
T25 2084 0 0 1
T36 0 924 0 0
T37 0 1583 0 0
T40 0 2025 0 0
T43 0 1693 0 0
T44 0 952 0 0
T51 0 997 0 0
T88 0 613 0 0
T89 0 133 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 262473 0 0
T1 2202 117 0 0
T2 2940 0 0 0
T3 4388 0 0 0
T4 508 0 0 0
T5 26607 0 0 0
T6 2027 0 0 0
T10 2590 0 0 0
T11 3730 0 0 0
T12 0 1706 0 0
T24 338039 0 0 0
T25 2084 0 0 0
T36 0 924 0 0
T37 0 1583 0 0
T40 0 2025 0 0
T43 0 1693 0 0
T44 0 952 0 0
T51 0 997 0 0
T88 0 613 0 0
T89 0 133 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT38,T36,T37

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT38,T36,T37
10CoveredT38,T36,T37
11CoveredT38,T36,T37

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T36,T37

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT38,T36,T37

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT38,T36,T37
11CoveredT38,T36,T37

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T36,T37

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T36,T37

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T36,T37

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T36,T37

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT38,T36,T37
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT92,T233,T210
11CoveredT38,T36,T37

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT38,T36,T37
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T38,T36,T37
0 0 1 Covered T38,T36,T37
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T38,T36,T37
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T38,T36,T37
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 250960 0 964
ValidOPairedWithReadyI_A 220552487 250960 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 250960 0 964
T7 2416 0 0 1
T12 0 1101 0 0
T21 0 844 0 0
T29 2062 0 0 1
T34 316295 0 0 1
T36 1665 939 0 1
T37 2382 1338 0 1
T38 1483 869 0 1
T40 0 1594 0 0
T46 0 1278 0 0
T53 966 0 0 1
T78 1890 0 0 1
T79 1391 0 0 1
T90 0 1572 0 0
T91 0 950 0 0
T92 0 663 0 0
T93 3951 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 250960 0 0
T7 2416 0 0 0
T12 0 1101 0 0
T21 0 844 0 0
T29 2062 0 0 0
T34 316295 0 0 0
T36 1665 939 0 0
T37 2382 1338 0 0
T38 1483 869 0 0
T40 0 1594 0 0
T46 0 1278 0 0
T53 966 0 0 0
T78 1890 0 0 0
T79 1391 0 0 0
T90 0 1572 0 0
T91 0 950 0 0
T92 0 663 0 0
T93 3951 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT37,T12,T39

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT37,T12,T39
10CoveredT37,T12,T39
11CoveredT37,T12,T39

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT37,T12,T39

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT37,T12,T39

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT37,T12,T39
11CoveredT37,T12,T39

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT37,T12,T39

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT37,T12,T39

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT37,T12,T39

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT37,T12,T39

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT37,T12,T39
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT104,T173,T234
11CoveredT37,T12,T39

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT37,T12,T39
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T37,T12,T39
0 0 1 Covered T37,T12,T39
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T12,T39
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T12,T39
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 226759 0 964
ValidOPairedWithReadyI_A 220552487 226759 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 226759 0 964
T12 0 1593 0 0
T15 2547 0 0 1
T26 977 0 0 1
T29 2062 0 0 1
T37 2382 1367 0 1
T39 0 895 0 0
T40 0 1642 0 0
T43 0 3049 0 0
T44 0 1303 0 0
T46 3171 0 0 1
T47 0 1764 0 0
T48 0 892 0 0
T75 1834 0 0 1
T78 1890 0 0 1
T79 1391 0 0 1
T87 0 1923 0 0
T93 3951 0 0 1
T94 0 861 0 0
T95 1950 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 226759 0 0
T12 0 1593 0 0
T15 2547 0 0 0
T26 977 0 0 0
T29 2062 0 0 0
T37 2382 1367 0 0
T39 0 895 0 0
T40 0 1642 0 0
T43 0 3049 0 0
T44 0 1303 0 0
T46 3171 0 0 0
T47 0 1764 0 0
T48 0 892 0 0
T75 1834 0 0 0
T78 1890 0 0 0
T79 1391 0 0 0
T87 0 1923 0 0
T93 3951 0 0 0
T94 0 861 0 0
T95 1950 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT40,T41,T23

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT40,T41,T23
10CoveredT40,T41,T23
11CoveredT40,T41,T23

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T41,T23

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT40,T41,T23

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT40,T41,T23
11CoveredT40,T41,T23

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T41,T23

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T41,T23

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T41,T23

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T41,T23

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT40,T41,T23
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT235,T201,T236
11CoveredT40,T41,T23

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT40,T41,T23
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T40,T41,T23
0 0 1 Covered T40,T41,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T40,T41,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T40,T41,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 204222 0 964
ValidOPairedWithReadyI_A 220552487 204222 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 204222 0 964
T16 1938 0 0 1
T22 4410 0 0 1
T23 6673 6085 0 1
T40 2219 1551 0 1
T41 2061 1372 0 1
T47 0 2132 0 0
T48 0 1075 0 0
T49 0 1055 0 0
T59 1010 0 0 1
T60 1912 0 0 1
T76 249608 0 0 1
T88 1239 0 0 1
T96 0 3609 0 0
T97 0 2137 0 0
T98 0 1133 0 0
T99 0 2196 0 0
T100 784 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 204222 0 0
T16 1938 0 0 0
T22 4410 0 0 0
T23 6673 6085 0 0
T40 2219 1551 0 0
T41 2061 1372 0 0
T47 0 2132 0 0
T48 0 1075 0 0
T49 0 1055 0 0
T59 1010 0 0 0
T60 1912 0 0 0
T76 249608 0 0 0
T88 1239 0 0 0
T96 0 3609 0 0
T97 0 2137 0 0
T98 0 1133 0 0
T99 0 2196 0 0
T100 784 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT38,T12,T50

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT38,T12,T50
10CoveredT38,T12,T50
11CoveredT38,T12,T50

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T12,T50

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT38,T12,T50

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT38,T12,T50
11CoveredT38,T12,T50

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T12,T50

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T12,T50

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T12,T50

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T12,T50

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT38,T12,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT50,T51,T102
11CoveredT38,T12,T50

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT38,T12,T50
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T38,T12,T50
0 0 1 Covered T38,T12,T50
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T38,T12,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T38,T12,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 220552487 165440 0 964
ValidOPairedWithReadyI_A 220552487 165440 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 165440 0 964
T7 2416 0 0 1
T12 0 1518 0 0
T29 2062 0 0 1
T34 316295 0 0 1
T36 1665 0 0 1
T37 2382 0 0 1
T38 1483 898 0 1
T41 0 1537 0 0
T44 0 1294 0 0
T45 0 1430 0 0
T50 0 116 0 0
T51 0 126 0 0
T53 966 0 0 1
T78 1890 0 0 1
T79 1391 0 0 1
T87 0 2115 0 0
T93 3951 0 0 1
T101 0 657 0 0
T102 0 118 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220552487 165440 0 0
T7 2416 0 0 0
T12 0 1518 0 0
T29 2062 0 0 0
T34 316295 0 0 0
T36 1665 0 0 0
T37 2382 0 0 0
T38 1483 898 0 0
T41 0 1537 0 0
T44 0 1294 0 0
T45 0 1430 0 0
T50 0 116 0 0
T51 0 126 0 0
T53 966 0 0 0
T78 1890 0 0 0
T79 1391 0 0 0
T87 0 2115 0 0
T93 3951 0 0 0
T101 0 657 0 0
T102 0 118 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%