Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.16	98.25	93.67	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.06	99.92	92.32	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T23,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T4,T5,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T23	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T6	Yes	T3,T10,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
tl_i.a_source[7:0]	Yes	Yes	T3,T23,T5	Yes	T3,T23,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T47,T48	Yes	T6,T47,T48	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T23,T4	Yes	T2,T3,T23	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T5,T26,T34	Yes	T5,T26,T34	INPUT
edn_i[2].edn_req	Yes	Yes	T23,T10,T34	Yes	T23,T10,T34	INPUT
edn_i[3].edn_req	Yes	Yes	T34,T49,T16	Yes	T34,T49,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T50,T32,T7	Yes	T50,T32,T7	INPUT
edn_i[5].edn_req	Yes	Yes	T26,T34,T51	Yes	T26,T34,T51	INPUT
edn_i[6].edn_req	Yes	Yes	T26,T11,T34	Yes	T26,T11,T34	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T6,T35	Yes	T4,T6,T11	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T34,T29	Yes	T26,T34,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T34,T49,T14	Yes	T26,T34,T49	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T34,T29	Yes	T26,T34,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T23,T10,T34	Yes	T23,T10,T34	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T51,T52,T53	Yes	T34,T12,T51	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T10,T34	Yes	T23,T10,T34	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T34,T49,T51	Yes	T34,T49,T51	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T34,T49,T51	Yes	T34,T49,T51	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T34,T49,T51	Yes	T34,T49,T51	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T32,T7,T52	Yes	T32,T7,T52	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T7,T54,T55	Yes	T50,T7,T52	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T50,T32,T52	Yes	T50,T32,T52	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T26,T34,T51	Yes	T26,T34,T51	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T26,T14,T56	Yes	T26,T51,T14	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T26,T34,T51	Yes	T26,T34,T51	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T26,T34,T54	Yes	T26,T11,T34	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T26,T34,T54	Yes	T26,T11,T34	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T26,T11,T34	Yes	T26,T11,T34	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T26,T6,T11	Yes	T3,T26,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T26,T10,T6	Yes	T26,T10,T6	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T23,T29,T32	Yes	T23,T29,T32	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T24,T29	Yes	T23,T24,T29	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T24,T29	Yes	T23,T24,T29	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T47,T57	Yes	T6,T47,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T47	Yes	T4,T6,T47	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	198499533	198344652	0	0
CsrngAppIfOut_A	198499533	198344652	0	0
FpvSecCmCntAlertCheck_A	198499533	92	0	0
FpvSecCmGenCmdFifoRptrCheck_A	198499533	50	0	0
FpvSecCmGenCmdFifoWptrCheck_A	198499533	50	0	0
FpvSecCmMainFsmCheck_A	198499533	50	0	0
FpvSecCmRegWeOnehotCheck_A	198499533	50	0	0
FpvSecCmResCmdFifoRptrCheck_A	198499533	50	0	0
FpvSecCmResCmdFifoWptrCheck_A	198499533	50	0	0
IntrEdnCmdReqDoneKnownO_A	198499533	198344652	0	0
TlAReadyKnownO_A	198499533	198344652	0	0
TlDValidKnownO_A	198499533	198344652	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	198499533	50	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[0].EdnDataStable_A	198499533	23742	0	425
gen_edn_if_asserts[0].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[1].EdnDataStable_A	198499533	6527	0	144
gen_edn_if_asserts[1].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[2].EdnDataStable_A	198499533	4275	0	126
gen_edn_if_asserts[2].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[3].EdnDataStable_A	198499533	53820	0	110
gen_edn_if_asserts[3].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[4].EdnDataStable_A	198499533	2777	0	92
gen_edn_if_asserts[4].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[5].EdnDataStable_A	198499533	3182	0	99
gen_edn_if_asserts[5].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	198499533	128868	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	198499533	548382	0	320
gen_edn_if_asserts[6].EdnDataStable_A	198499533	3778	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	198499533	198344652	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	198499533	128868	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	92	0	0
T7	0	1	0	0
T16	967	1	0	0
T17	1882	1	0	0
T18	0	10	0	0
T21	3169	0	0	0
T30	2471	0	0	0
T42	1768	0	0	0
T44	513	0	0	0
T47	902983	0	0	0
T48	332194	0	0	0
T57	8984	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1225	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	50	0	0
T18	24900	10	0	0
T19	0	10	0	0
T20	0	10	0	0
T61	1722	0	0	0
T65	0	10	0	0
T66	0	10	0	0
T67	3775	0	0	0
T68	240872	0	0	0
T69	6347	0	0	0
T70	6017	0	0	0
T71	1781	0	0	0
T72	1981	0	0	0
T73	7957	0	0	0
T74	2108	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	23742	0	425
T1	1014	3	0	1
T2	1410	3	0	1
T3	1876	7	0	1
T4	1953	1	0	0
T5	893	0	0	0
T6	0	100	0	0
T10	2419	0	0	0
T11	0	1	0	0
T23	1778	0	0	0
T24	1880	0	0	0
T25	887	3	0	1
T26	1960	0	0	0
T33	0	3	0	1
T34	0	3	0	1
T35	0	53	0	1
T36	0	0	0	1
T37	0	0	0	1
T76	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	6527	0	144
T6	229442	0	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T14	0	63	0	1
T26	1960	3	0	1
T29	2881	4	0	1
T33	1062	0	0	0
T34	2498	78	0	1
T35	1233	0	0	0
T36	1677	0	0	0
T49	0	19	0	1
T52	0	48	0	1
T81	0	3	0	1
T82	0	399	0	1
T83	0	663	0	1
T84	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	4275	0	126
T4	1953	0	0	0
T5	893	0	0	0
T6	229442	0	0	0
T10	2419	4	0	0
T11	3650	0	0	0
T12	0	4	0	0
T14	0	3	0	1
T21	0	4	0	0
T23	1778	4	0	1
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T32	0	4	0	0
T33	1062	0	0	0
T34	0	3	0	1
T51	0	40	0	1
T52	0	42	0	1
T54	0	3	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	53820	0	110
T12	2456	0	0	0
T29	2881	0	0	0
T34	2498	62	0	1
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T49	0	58	0	1
T50	1052	0	0	0
T51	0	35	0	1
T52	0	15	0	1
T56	0	3	0	1
T76	1651	0	0	0
T84	0	3	0	1
T85	0	3	0	1
T86	0	3	0	1
T88	0	4	0	0
T89	0	4	0	0
T90	3450	0	0	0
T91	1794	0	0	0
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	2777	0	92
T9	0	1	0	0
T16	967	0	0	0
T32	0	4	0	1
T42	1768	0	0	0
T44	513	0	0	0
T47	902983	0	0	0
T49	1597	0	0	0
T50	1052	3	0	1
T52	0	3	0	1
T54	0	51	0	1
T55	0	49	0	1
T76	1651	0	0	0
T84	0	3	0	1
T89	0	4	0	1
T90	3450	0	0	0
T91	1794	0	0	0
T94	0	3	0	1
T95	0	4	0	1
T96	2383	0	0	0
T97	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	3182	0	99
T6	229442	0	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T14	0	31	0	1
T26	1960	61	0	1
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	3	0	1
T35	1233	0	0	0
T36	1677	0	0	0
T51	0	19	0	1
T52	0	3	0	1
T56	0	8	0	1
T84	0	3	0	1
T86	0	53	0	1
T94	0	0	0	1
T98	0	1	0	0
T99	0	1	0	0
T100	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	548382	0	320
T1	1014	13	0	0
T2	1410	67	0	0
T3	1876	37	0	0
T4	1953	939	0	0
T5	893	401	0	0
T6	0	0	0	2
T10	2419	1474	0	2
T11	0	0	0	2
T12	0	0	0	2
T21	0	0	0	2
T23	1778	169	0	0
T24	1880	1818	0	2
T25	887	15	0	0
T26	1960	125	0	0
T47	0	0	0	2
T48	0	0	0	2
T57	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	3778	0	84
T6	229442	0	0	0
T10	2419	0	0	0
T11	3650	4	0	0
T12	2456	0	0	0
T26	1960	44	0	1
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	47	0	1
T35	1233	0	0	0
T36	1677	0	0	0
T54	0	39	0	1
T56	0	3	0	1
T84	0	3	0	1
T85	0	1165	0	1
T94	0	65	0	1
T101	0	4	0	1
T102	0	4	0	1
T103	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	128868	0	0
T4	1953	24	0	0
T5	893	433	0	0
T6	229442	0	0	0
T7	0	464	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	574	0	0
T17	0	1163	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T44	0	200	0	0
T77	0	1107	0	0
T78	0	413	0	0
T79	0	352	0	0
T80	0	666	0	0