Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	199046050	8962234	0	0
boot_gen_cmd_rd_A	199046050	46109	0	0
boot_ins_cmd_rd_A	199046050	51851	0	0
ctrl_rd_A	199046050	45561	0	0
err_code_test_rd_A	199046050	52056	0	0
intr_enable_rd_A	199046050	52087	0	0
max_num_reqs_between_reseeds_rd_A	199046050	45482	0	0
regwen_rd_A	199046050	53870	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	8962234	0	0
T6	229442	75305	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T47	0	36601	0	0
T48	0	126932	0	0
T50	1052	0	0	0
T68	0	94864	0	0
T106	0	290365	0	0
T234	0	166487	0	0
T235	0	91706	0	0
T236	0	105372	0	0
T237	0	259629	0	0
T238	0	77939	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	46109	0	0
T6	229442	2294	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	1928	0	0
T50	1052	0	0	0
T239	0	1615	0	0
T240	0	784	0	0
T241	0	3658	0	0
T242	0	7251	0	0
T243	0	8205	0	0
T244	0	1612	0	0
T245	0	1675	0	0
T246	0	8881	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	51851	0	0
T6	229442	2479	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	2396	0	0
T50	1052	0	0	0
T239	0	1983	0	0
T240	0	990	0	0
T241	0	3960	0	0
T242	0	7739	0	0
T243	0	8986	0	0
T244	0	1800	0	0
T245	0	1657	0	0
T246	0	10292	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	45561	0	0
T2	1410	3	0	0
T3	1876	0	0	0
T4	1953	0	0	0
T5	893	0	0	0
T6	229442	2271	0	0
T10	2419	0	0	0
T23	1778	0	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T48	0	1696	0	0
T78	0	6	0	0
T239	0	1578	0	0
T240	0	1029	0	0
T241	0	3753	0	0
T247	0	8	0	0
T248	0	2	0	0
T249	0	9	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	52056	0	0
T6	229442	2386	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	2213	0	0
T50	1052	0	0	0
T239	0	1843	0	0
T240	0	841	0	0
T241	0	3980	0	0
T242	0	7863	0	0
T243	0	9163	0	0
T244	0	1864	0	0
T245	0	2047	0	0
T246	0	10377	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	52087	0	0
T6	229442	2524	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	2198	0	0
T50	1052	0	0	0
T57	0	43	0	0
T239	0	2211	0	0
T240	0	944	0	0
T250	0	84	0	0
T251	0	17	0	0
T252	0	18	0	0
T253	0	8	0	0
T254	0	101	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	45482	0	0
T6	229442	1954	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	1910	0	0
T50	1052	0	0	0
T239	0	1812	0	0
T240	0	873	0	0
T241	0	3521	0	0
T242	0	6686	0	0
T243	0	7532	0	0
T244	0	1686	0	0
T245	0	1564	0	0
T246	0	8724	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199046050	53870	0	0
T6	229442	2591	0	0
T11	3650	0	0	0
T12	2456	0	0	0
T29	2881	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0
T48	0	2513	0	0
T50	1052	0	0	0
T239	0	2142	0	0
T240	0	933	0	0
T241	0	4189	0	0
T242	0	7754	0	0
T243	0	8995	0	0
T244	0	1843	0	0
T245	0	1812	0	0
T246	0	10416	0	0