Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.38	98.25	93.85	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.29	99.92	92.58	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T16,T17
1	0	Covered	T5,T30,T14

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T4,T38	Yes	T3,T4,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T5,T39,T40	Yes	T5,T39,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T28,T40,T41	Yes	T28,T40,T41	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T13,T42	Yes	T2,T13,T42	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T22,T43	Yes	T2,T22,T43	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T28,T44	Yes	T2,T28,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T4,T27	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T39,T40,T45	Yes	T39,T40,T46	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T39,T45,T47	Yes	T39,T40,T46	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T39,T40,T46	Yes	T39,T40,T46	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T28,T40,T41	Yes	T28,T40,T41	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T11,T48	Yes	T28,T41,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T28,T40,T41	Yes	T28,T40,T41	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T2,T8,T40	Yes	T2,T8,T9	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T13,T40	Yes	T2,T13,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T2,T20,T11	Yes	T2,T49,T20	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T13,T42	Yes	T2,T13,T42	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T43,T50	Yes	T2,T22,T43	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T51,T10	Yes	T2,T22,T43	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T22,T43	Yes	T2,T22,T43	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T28,T20	Yes	T2,T28,T44	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T20,T10,T52	Yes	T2,T44,T20	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T28,T44	Yes	T2,T28,T44	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T27,T43,T41	Yes	T27,T43,T41	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T27,T53	Yes	T8,T27,T53	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T53,T30	Yes	T5,T53,T30	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T27,T53	Yes	T8,T27,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T53,T30	Yes	T5,T53,T30	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T4,T38	Yes	T3,T4,T38	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T38	Yes	T3,T4,T38	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	206353586	206165186	0	0
CsrngAppIfOut_A	206353586	206165186	0	0
FpvSecCmCntAlertCheck_A	206353586	136	0	0
FpvSecCmGenCmdFifoRptrCheck_A	206353586	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	206353586	80	0	0
FpvSecCmMainFsmCheck_A	206353586	80	0	0
FpvSecCmRegWeOnehotCheck_A	206353586	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	206353586	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	206353586	80	0	0
IntrEdnCmdReqDoneKnownO_A	206353586	206165186	0	0
TlAReadyKnownO_A	206353586	206165186	0	0
TlDValidKnownO_A	206353586	206165186	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	206353586	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[0].EdnDataStable_A	206353586	22971	0	410
gen_edn_if_asserts[0].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[1].EdnDataStable_A	206353586	5940	0	140
gen_edn_if_asserts[1].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[2].EdnDataStable_A	206353586	4808	0	132
gen_edn_if_asserts[2].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[3].EdnDataStable_A	206353586	4305	0	129
gen_edn_if_asserts[3].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[4].EdnDataStable_A	206353586	4147	0	112
gen_edn_if_asserts[4].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[5].EdnDataStable_A	206353586	2776	0	103
gen_edn_if_asserts[5].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	206353586	161296	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	206353586	567126	0	328
gen_edn_if_asserts[6].EdnDataStable_A	206353586	5397	0	86
gen_edn_if_asserts[6].EdnEndPointOut_A	206353586	206165186	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	206353586	161296	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	136	0	0
T5	2199	1	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	20	0	0
T15	0	1	0	0
T16	0	10	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	236047	0	0	0
T61	1655	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	80	0	0
T14	44390	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T18	4272	0	0	0
T41	2174	0	0	0
T45	3713	0	0	0
T50	2374	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2605	0	0	0
T65	1752	0	0	0
T66	2161	0	0	0
T67	15334	0	0	0
T68	1351	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	22971	0	410
T1	1750	7	0	1
T2	1622	7	0	1
T3	630663	188	0	0
T4	432802	87	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	3	0	1
T27	0	8	0	1
T38	0	91	0	0
T40	0	0	0	1
T60	0	72	0	0
T70	0	7	0	1
T71	0	3	0	1
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	5940	0	140
T10	0	56	0	1
T11	0	38	0	1
T20	0	3	0	1
T21	2600	0	0	0
T39	4558	13	0	1
T40	3339	3	0	1
T43	4079	0	0	0
T44	0	3	0	1
T45	0	366	0	1
T46	2805	3	0	1
T47	0	41	0	1
T69	708471	0	0	0
T71	1304	0	0	0
T72	17814	0	0	0
T73	1803	0	0	0
T74	1683	0	0	0
T75	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	4808	0	132
T10	0	23	0	1
T11	0	27	0	1
T18	0	4	0	0
T20	0	3	0	1
T21	2600	0	0	0
T28	2718	4	0	1
T30	738	0	0	0
T39	4558	0	0	0
T40	0	3	0	1
T41	0	4	0	1
T42	1017	0	0	0
T43	4079	0	0	0
T44	0	3	0	1
T70	4901	0	0	0
T71	1304	0	0	0
T72	17814	0	0	0
T73	1803	0	0	0
T75	0	13	0	1
T76	0	4	0	0
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	4305	0	129
T2	1622	47	0	1
T3	630663	0	0	0
T4	432802	0	0	0
T5	2199	0	0	0
T8	1949	8	0	1
T9	3370	4	0	0
T13	1862	0	0	0
T20	0	453	0	1
T21	0	4	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T30	0	1	0	0
T40	0	59	0	1
T47	0	43	0	1
T51	0	0	0	1
T61	0	3	0	1
T75	0	0	0	1
T79	0	4	0	0
T80	0	0	0	1
T81	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	4147	0	112
T2	1622	27	0	1
T3	630663	0	0	0
T4	432802	0	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T10	0	3	0	1
T11	0	28	0	1
T13	1862	4	0	0
T19	0	4	0	0
T20	0	62	0	1
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T40	0	3	0	1
T42	0	4	0	0
T49	0	4	0	1
T52	0	0	0	1
T82	0	3	0	1
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	2776	0	103
T2	1622	32	0	1
T3	630663	0	0	0
T4	432802	0	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T10	0	15	0	1
T11	0	43	0	1
T13	1862	0	0	0
T19	0	1	0	0
T22	1139	3	0	1
T23	992	0	0	0
T27	2012	0	0	0
T43	0	4	0	1
T50	0	4	0	0
T51	0	33	0	1
T85	0	4	0	0
T86	0	4	0	0
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1
T90	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	567126	0	328
T1	1750	53	0	0
T2	1622	16	0	0
T3	630663	2005	0	2
T4	432802	2203	0	2
T5	2199	1456	0	0
T8	1949	341	0	0
T9	3370	1640	0	2
T13	1862	580	0	2
T14	0	0	0	2
T21	0	0	0	2
T22	1139	57	0	0
T23	992	37	0	0
T38	0	0	0	2
T53	0	0	0	2
T60	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	5397	0	86
T2	1622	3	0	1
T3	630663	0	0	0
T4	432802	0	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T10	0	27	0	1
T13	1862	0	0	0
T20	0	63	0	1
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T28	0	4	0	0
T44	0	3	0	1
T52	0	34	0	1
T90	0	32	0	1
T91	0	4	0	0
T92	0	4	0	1
T93	0	4	0	1
T94	0	0	0	1
T95	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	161296	0	0
T5	2199	1100	0	0
T6	0	804	0	0
T7	0	231	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15401	0	0
T15	0	1133	0	0
T23	992	0	0	0
T27	2012	0	0	0
T29	0	29	0	0
T30	0	7	0	0
T31	0	7	0	0
T32	0	654	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1124	0	0
T60	236047	0	0	0
T61	1655	0	0	0