Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	206938611	9252479	0	0
boot_gen_cmd_rd_A	206938611	51037	0	0
boot_ins_cmd_rd_A	206938611	57894	0	0
ctrl_rd_A	206938611	49302	0	0
err_code_test_rd_A	206938611	57880	0	0
intr_enable_rd_A	206938611	55184	0	0
max_num_reqs_between_reseeds_rd_A	206938611	51069	0	0
regwen_rd_A	206938611	57867	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	9252479	0	0
T3	630663	260570	0	0
T4	432802	142283	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	236066	0	0
T60	0	96730	0	0
T69	0	396958	0	0
T226	0	162260	0	0
T227	0	115657	0	0
T228	0	190613	0	0
T229	0	228383	0	0
T230	0	94140	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	51037	0	0
T4	432802	3994	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	6996	0	0
T60	236047	0	0	0
T226	0	4939	0	0
T231	0	1474	0	0
T232	0	1262	0	0
T233	0	1437	0	0
T234	0	5415	0	0
T235	0	6053	0	0
T236	0	5874	0	0
T237	0	1829	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	57894	0	0
T4	432802	4830	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	7663	0	0
T60	236047	0	0	0
T226	0	5179	0	0
T231	0	1599	0	0
T232	0	1318	0	0
T233	0	1652	0	0
T234	0	5976	0	0
T235	0	7187	0	0
T236	0	7100	0	0
T237	0	2301	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	49302	0	0
T4	432802	3888	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	6709	0	0
T54	0	1	0	0
T60	236047	0	0	0
T64	0	7	0	0
T67	0	3	0	0
T150	0	8	0	0
T226	0	4092	0	0
T231	0	1279	0	0
T232	0	1119	0	0
T233	0	1341	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	57880	0	0
T4	432802	4647	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	7907	0	0
T60	236047	0	0	0
T226	0	5377	0	0
T231	0	1797	0	0
T232	0	1321	0	0
T233	0	1609	0	0
T234	0	6096	0	0
T235	0	7265	0	0
T236	0	6758	0	0
T237	0	2259	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	55184	0	0
T4	432802	4248	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	6960	0	0
T60	236047	0	0	0
T67	0	20	0	0
T72	0	40	0	0
T226	0	4932	0	0
T231	0	1607	0	0
T232	0	1521	0	0
T233	0	1475	0	0
T238	0	18	0	0
T239	0	95	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	51069	0	0
T4	432802	3993	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	6782	0	0
T60	236047	0	0	0
T226	0	4696	0	0
T231	0	1481	0	0
T232	0	1110	0	0
T233	0	1256	0	0
T234	0	5766	0	0
T235	0	6132	0	0
T236	0	6017	0	0
T237	0	2043	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206938611	57867	0	0
T4	432802	4896	0	0
T5	2199	0	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T22	1139	0	0	0
T23	992	0	0	0
T27	2012	0	0	0
T38	704299	7566	0	0
T60	236047	0	0	0
T226	0	5057	0	0
T231	0	1599	0	0
T232	0	1278	0	0
T233	0	1453	0	0
T234	0	6327	0	0
T235	0	6783	0	0
T236	0	6725	0	0
T237	0	2323	0	0