Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 98.25 93.97 97.02 92.44 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 94.23 99.92 92.75 82.54 92.44 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T14,T9

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT1,T4,T5

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T20 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T21,T15,T31 Yes T21,T15,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T20 Yes T1,T2,T20 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T31,T32,T33 Yes T31,T32,T33 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T20 Yes T1,T2,T20 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[1].edn_req Yes Yes T3,T21,T13 Yes T3,T21,T13 INPUT
edn_i[2].edn_req Yes Yes T3,T21,T13 Yes T3,T21,T13 INPUT
edn_i[3].edn_req Yes Yes T3,T13,T10 Yes T3,T13,T10 INPUT
edn_i[4].edn_req Yes Yes T3,T14,T13 Yes T3,T14,T13 INPUT
edn_i[5].edn_req Yes Yes T3,T13,T10 Yes T3,T13,T10 INPUT
edn_i[6].edn_req Yes Yes T3,T10,T34 Yes T3,T10,T34 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
edn_o[0].edn_fips Yes Yes T1,T21,T13 Yes T1,T2,T21 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T3,T21,T13 Yes T3,T21,T13 OUTPUT
edn_o[1].edn_fips Yes Yes T21,T13,T19 Yes T3,T21,T13 OUTPUT
edn_o[1].edn_ack Yes Yes T3,T21,T13 Yes T3,T21,T13 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T3,T21,T13 Yes T3,T21,T13 OUTPUT
edn_o[2].edn_fips Yes Yes T3,T13,T10 Yes T3,T13,T10 OUTPUT
edn_o[2].edn_ack Yes Yes T3,T21,T13 Yes T3,T21,T13 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T3,T13,T10 Yes T3,T13,T10 OUTPUT
edn_o[3].edn_fips Yes Yes T35,T36,T37 Yes T3,T13,T35 OUTPUT
edn_o[3].edn_ack Yes Yes T3,T13,T10 Yes T3,T13,T10 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T3,T10,T35 Yes T3,T10,T35 OUTPUT
edn_o[4].edn_fips Yes Yes T3,T10,T35 Yes T3,T10,T35 OUTPUT
edn_o[4].edn_ack Yes Yes T3,T13,T10 Yes T3,T13,T10 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T3,T10,T25 Yes T3,T10,T25 OUTPUT
edn_o[5].edn_fips Yes Yes T3,T38,T39 Yes T3,T10,T40 OUTPUT
edn_o[5].edn_ack Yes Yes T3,T13,T10 Yes T3,T13,T10 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T3,T10,T34 Yes T3,T10,T34 OUTPUT
edn_o[6].edn_fips Yes Yes T3,T10,T37 Yes T3,T10,T41 OUTPUT
edn_o[6].edn_ack Yes Yes T3,T10,T34 Yes T3,T10,T34 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T21 Yes T3,T21,T13 INPUT
csrng_cmd_i.genbits_fips Yes Yes T3,T21,T13 Yes T2,T3,T21 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T2,T14,T42 Yes T2,T14,T42 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T14,T9 Yes T2,T14,T9 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T14,T9 Yes T2,T14,T9 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T31,T43,T32 Yes T31,T43,T32 OUTPUT
intr_edn_fatal_err_o Yes Yes T1,T5,T31 Yes T1,T5,T31 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 207882566 207704768 0 0
CsrngAppIfOut_A 207882566 207704768 0 0
FpvSecCmCntAlertCheck_A 207882566 112 0 0
FpvSecCmGenCmdFifoRptrCheck_A 207882566 70 0 0
FpvSecCmGenCmdFifoWptrCheck_A 207882566 70 0 0
FpvSecCmMainFsmCheck_A 207882566 70 0 0
FpvSecCmRegWeOnehotCheck_A 207882566 70 0 0
FpvSecCmResCmdFifoRptrCheck_A 207882566 70 0 0
FpvSecCmResCmdFifoWptrCheck_A 207882566 70 0 0
IntrEdnCmdReqDoneKnownO_A 207882566 207704768 0 0
TlAReadyKnownO_A 207882566 207704768 0 0
TlDValidKnownO_A 207882566 207704768 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 207882566 70 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[0].EdnDataStable_A 207882566 117881 0 428
gen_edn_if_asserts[0].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[1].EdnDataStable_A 207882566 3979 0 129
gen_edn_if_asserts[1].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[2].EdnDataStable_A 207882566 4053 0 112
gen_edn_if_asserts[2].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[3].EdnDataStable_A 207882566 6755 0 119
gen_edn_if_asserts[3].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[4].EdnDataStable_A 207882566 51129 0 94
gen_edn_if_asserts[4].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[5].EdnDataStable_A 207882566 4314 0 85
gen_edn_if_asserts[5].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 207882566 137111 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 207882566 562426 0 326
gen_edn_if_asserts[6].EdnDataStable_A 207882566 52547 0 95
gen_edn_if_asserts[6].EdnEndPointOut_A 207882566 207704768 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 207882566 137111 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 112 0 0
T7 0 1 0 0
T9 2818 0 0 0
T10 4144 0 0 0
T13 3955 0 0 0
T14 579 1 0 0
T15 773 1 0 0
T16 0 20 0 0
T19 4956 0 0 0
T31 140408 0 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 1812 0 0 0
T51 743 0 0 0
T52 4079 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 70 0 0
T16 46776 20 0 0
T17 0 10 0 0
T18 0 20 0 0
T26 1964 0 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1213 0 0 0
T56 2200 0 0 0
T57 1074 0 0 0
T58 2762 0 0 0
T59 2320 0 0 0
T60 2228 0 0 0
T61 1677 0 0 0
T62 2325 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 117881 0 428
T1 1371 1 0 0
T2 1826 4 0 1
T3 4429 3 0 1
T4 710 0 0 0
T5 672 1 0 0
T9 0 0 0 1
T10 0 39 0 1
T13 3955 57 0 1
T14 579 0 0 0
T15 773 0 0 0
T20 1083 3 0 1
T21 2221 16 0 1
T31 0 111 0 0
T50 0 39 0 1
T52 0 0 0 1
T72 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 3979 0 129
T3 4429 3 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 0 0 0
T13 3955 42 0 1
T14 579 0 0 0
T15 773 0 0 0
T19 4956 61 0 1
T20 1083 0 0 0
T21 2221 15 0 1
T35 0 13 0 1
T40 0 0 0 1
T51 0 4 0 0
T66 0 4 0 0
T74 0 3 0 1
T75 0 4 0 0
T76 0 4 0 0
T77 0 0 0 1
T78 0 0 0 1
T79 0 0 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 4053 0 112
T3 4429 21 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 53 0 1
T13 3955 28 0 1
T14 579 0 0 0
T15 773 0 0 0
T19 4956 3 0 1
T20 1083 0 0 0
T21 2221 3 0 1
T35 0 7 0 1
T36 0 22 0 1
T70 0 4 0 0
T75 0 4 0 1
T76 0 4 0 1
T77 0 0 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 6755 0 119
T3 4429 3 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 3 0 1
T13 3955 31 0 1
T14 579 0 0 0
T15 773 0 0 0
T19 4956 0 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T35 0 5 0 1
T36 0 40 0 1
T37 0 7 0 1
T40 0 45 0 1
T64 0 4 0 0
T77 0 3 0 1
T79 0 0 0 1
T80 0 4 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 51129 0 94
T3 4429 159 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 59 0 1
T13 3955 3 0 1
T14 579 0 0 0
T15 773 0 0 0
T19 4956 0 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T35 0 52 0 1
T37 0 3 0 1
T39 0 0 0 1
T40 0 0 0 1
T41 0 4 0 0
T67 0 4 0 0
T71 0 4 0 0
T77 0 3 0 1
T81 0 4 0 1
T82 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 4314 0 85
T3 4429 38 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 6 0 1
T13 3955 3 0 1
T14 579 0 0 0
T15 773 0 0 0
T19 4956 0 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T25 0 4 0 1
T37 0 3 0 1
T38 0 8 0 1
T39 0 60 0 1
T40 0 3 0 1
T77 0 3 0 1
T83 0 3 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 562426 0 326
T1 1371 585 0 0
T2 1826 201 0 0
T3 4429 341 0 0
T4 710 263 0 0
T5 672 278 0 0
T13 3955 456 0 0
T14 579 174 0 0
T15 773 327 0 0
T20 1083 120 0 0
T21 2221 31 0 0
T31 0 0 0 2
T63 0 0 0 2
T64 0 0 0 2
T65 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 52547 0 95
T3 4429 50 0 1
T4 710 0 0 0
T5 672 0 0 0
T10 4144 59 0 1
T13 3955 0 0 0
T14 579 0 0 0
T15 773 0 0 0
T19 4956 0 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T34 0 3 0 1
T37 0 22 0 1
T39 0 0 0 1
T40 0 20 0 1
T41 0 4 0 1
T71 0 4 0 0
T77 0 50 0 1
T82 0 0 0 1
T84 0 4 0 1
T85 0 4 0 0

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 207704768 0 0
T1 1371 1193 0 0
T2 1826 1740 0 0
T3 4429 4373 0 0
T4 710 518 0 0
T5 672 530 0 0
T13 3955 3905 0 0
T14 579 429 0 0
T15 773 641 0 0
T20 1083 987 0 0
T21 2221 2168 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 207882566 137111 0 0
T1 1371 36 0 0
T2 1826 0 0 0
T3 4429 0 0 0
T4 710 298 0 0
T5 672 7 0 0
T6 0 422 0 0
T7 0 414 0 0
T13 3955 0 0 0
T14 579 270 0 0
T15 773 408 0 0
T20 1083 0 0 0
T21 2221 0 0 0
T44 0 420 0 0
T45 0 1094 0 0
T73 0 1012 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%