Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	208368252	9390059	0	0
boot_gen_cmd_rd_A	208368252	47124	0	0
boot_ins_cmd_rd_A	208368252	53224	0	0
ctrl_rd_A	208368252	46544	0	0
err_code_test_rd_A	208368252	53111	0	0
intr_enable_rd_A	208368252	51772	0	0
max_num_reqs_between_reseeds_rd_A	208368252	46995	0	0
regwen_rd_A	208368252	53943	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	9390059	0	0
T6	1047	0	0	0
T9	2818	0	0	0
T31	140408	77029	0	0
T32	0	176682	0	0
T33	0	110510	0	0
T50	1812	0	0	0
T51	743	0	0	0
T52	4079	0	0	0
T63	2556	0	0	0
T64	1953	0	0	0
T72	1544	0	0	0
T97	0	92344	0	0
T223	0	396570	0	0
T224	0	131108	0	0
T225	0	97600	0	0
T226	0	77916	0	0
T227	0	179408	0	0
T228	0	115239	0	0
T229	1562	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	47124	0	0
T97	265691	2936	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3416	0	0
T230	0	3988	0	0
T231	0	2446	0	0
T232	0	7367	0	0
T233	0	3938	0	0
T234	0	3143	0	0
T235	0	5636	0	0
T236	0	9755	0	0
T237	0	4201	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	53224	0	0
T97	265691	3375	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3916	0	0
T230	0	4441	0	0
T231	0	2816	0	0
T232	0	8064	0	0
T233	0	4344	0	0
T234	0	3803	0	0
T235	0	6696	0	0
T236	0	10711	0	0
T237	0	4761	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	46544	0	0
T6	1047	0	0	0
T9	2818	6	0	0
T22	0	2	0	0
T25	2526	0	0	0
T29	0	6	0	0
T52	4079	0	0	0
T63	2556	0	0	0
T64	1953	0	0	0
T72	1544	0	0	0
T97	0	2741	0	0
T161	0	2	0	0
T228	0	3357	0	0
T229	1562	0	0	0
T230	0	3965	0	0
T243	0	15	0	0
T244	0	5	0	0
T245	0	5	0	0
T246	1029	0	0	0
T247	1647	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	53111	0	0
T97	265691	3349	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3726	0	0
T230	0	4479	0	0
T231	0	3188	0	0
T232	0	8146	0	0
T233	0	4291	0	0
T234	0	3540	0	0
T235	0	6650	0	0
T236	0	11037	0	0
T237	0	4450	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	51772	0	0
T97	265691	3338	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3549	0	0
T230	0	4269	0	0
T231	0	2817	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0
T248	0	41	0	0
T249	0	16	0	0
T250	0	96	0	0
T251	0	32	0	0
T252	0	93	0	0
T253	0	59	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	46995	0	0
T97	265691	2969	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3403	0	0
T230	0	4007	0	0
T231	0	2583	0	0
T232	0	7348	0	0
T233	0	4006	0	0
T234	0	3142	0	0
T235	0	5515	0	0
T236	0	9659	0	0
T237	0	3713	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208368252	53943	0	0
T97	265691	3636	0	0
T135	1956	0	0	0
T146	1530	0	0	0
T193	1068	0	0	0
T223	701288	0	0	0
T228	0	3880	0	0
T230	0	4669	0	0
T231	0	2788	0	0
T232	0	8468	0	0
T233	0	4327	0	0
T234	0	3802	0	0
T235	0	6550	0	0
T236	0	10719	0	0
T237	0	4426	0	0
T238	1005	0	0	0
T239	2776	0	0	0
T240	899	0	0	0
T241	1024	0	0	0
T242	4886	0	0	0