Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.25	93.97	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.03	99.92	92.75	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T19,T21,T22

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T14
1	0	Covered	T1,T2,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T21,T33,T11	Yes	T21,T33,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T18	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T18,T19	Yes	T1,T7,T18	INPUT
tl_i.a_source[7:0]	Yes	Yes	T19,T20,T21	Yes	T1,T3,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T7,T19	Yes	T3,T7,T19	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T19,T20	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T7,T20	Yes	T2,T7,T20	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
edn_i[2].edn_req	Yes	Yes	T7,T37,T17	Yes	T7,T37,T17	INPUT
edn_i[3].edn_req	Yes	Yes	T33,T12,T38	Yes	T33,T12,T38	INPUT
edn_i[4].edn_req	Yes	Yes	T7,T37,T39	Yes	T7,T37,T39	INPUT
edn_i[5].edn_req	Yes	Yes	T7,T33,T37	Yes	T7,T33,T37	INPUT
edn_i[6].edn_req	Yes	Yes	T37,T17,T40	Yes	T37,T17,T40	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T7,T20,T21	Yes	T7,T20,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T7,T20,T21	Yes	T7,T20,T21	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T7,T20,T21	Yes	T7,T20,T21	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T7,T18,T19	Yes	T3,T7,T18	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T37,T39,T41	Yes	T3,T19,T37	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T7,T18	Yes	T3,T7,T18	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T7,T42,T43	Yes	T7,T37,T17	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T7,T44,T45	Yes	T7,T44,T45	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T7,T37,T17	Yes	T7,T37,T17	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T33,T12,T46	Yes	T33,T12,T38	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T12,T39,T26	Yes	T12,T38,T39	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T33,T12,T38	Yes	T33,T12,T38	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T7,T37,T39	Yes	T7,T37,T39	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T7,T47,T48	Yes	T7,T37,T49	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T7,T37,T39	Yes	T7,T37,T39	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T7,T33,T37	Yes	T7,T33,T37	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T17,T41,T48	Yes	T37,T17,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T7,T33,T37	Yes	T7,T33,T37	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T17,T40,T50	Yes	T37,T17,T40	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T17,T40,T51	Yes	T17,T40,T52	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T37,T17,T40	Yes	T37,T17,T40	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T7,T20,T33	Yes	T3,T7,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T7,T20,T8	Yes	T7,T20,T37	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T3,T7,T18	Yes	T3,T7,T18	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T53,T54,T34	Yes	T53,T54,T34	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T53,T12,T54	Yes	T53,T12,T54	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	197283639	197082827	0	0
CsrngAppIfOut_A	197283639	197082827	0	0
FpvSecCmCntAlertCheck_A	197283639	137	0	0
FpvSecCmGenCmdFifoRptrCheck_A	197283639	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	197283639	90	0	0
FpvSecCmMainFsmCheck_A	197283639	90	0	0
FpvSecCmRegWeOnehotCheck_A	197283639	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	197283639	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	197283639	90	0	0
IntrEdnCmdReqDoneKnownO_A	197283639	197082827	0	0
TlAReadyKnownO_A	197283639	197082827	0	0
TlDValidKnownO_A	197283639	197082827	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	197283639	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[0].EdnDataStable_A	197283639	23291	0	435
gen_edn_if_asserts[0].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[1].EdnDataStable_A	197283639	7007	0	148
gen_edn_if_asserts[1].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[2].EdnDataStable_A	197283639	3699	0	130
gen_edn_if_asserts[2].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[3].EdnDataStable_A	197283639	52492	0	104
gen_edn_if_asserts[3].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[4].EdnDataStable_A	197283639	5649	0	117
gen_edn_if_asserts[4].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[5].EdnDataStable_A	197283639	3945	0	87
gen_edn_if_asserts[5].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	197283639	164543	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	197283639	597312	0	316
gen_edn_if_asserts[6].EdnDataStable_A	197283639	1250	0	81
gen_edn_if_asserts[6].EdnEndPointOut_A	197283639	197082827	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	197283639	164543	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	137	0	0
T5	2759	1	0	0
T6	0	1	0	0
T11	49473	20	0	0
T12	2212	1	0	0
T13	0	10	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	90	0	0
T5	2759	0	0	0
T11	49473	20	0	0
T12	2212	0	0	0
T13	0	10	0	0
T14	0	20	0	0
T15	2530	0	0	0
T37	3355	0	0	0
T38	1943	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	23291	0	435
T4	2661	1	0	0
T7	4704	55	0	1
T8	3235	4	0	0
T15	0	15	0	1
T17	0	0	0	1
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	35	0	1
T21	2878	8	0	1
T22	1550	4	0	1
T33	2317	0	0	0
T37	0	3	0	1
T53	16295	3	0	0
T62	0	1	0	0
T69	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	7007	0	148
T3	2613	4	0	0
T4	2661	0	0	0
T7	4704	3	0	1
T8	3235	0	0	0
T18	1119	3	0	1
T19	1980	4	0	1
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T33	2317	0	0	0
T37	0	35	0	1
T39	0	56	0	1
T44	0	0	0	1
T47	0	3	0	1
T50	0	3	0	1
T72	0	4	0	1
T73	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	3699	0	130
T4	2661	0	0	0
T7	4704	18	0	1
T8	3235	0	0	0
T17	0	3	0	1
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T33	2317	0	0	0
T37	0	3	0	1
T42	0	4	0	1
T43	0	4	0	1
T44	0	15	0	1
T45	0	49	0	1
T53	16295	0	0	0
T74	0	843	0	1
T75	0	20	0	1
T76	0	51	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	52492	0	104
T4	2661	0	0	0
T5	2759	0	0	0
T11	49473	0	0	0
T12	2212	1	0	0
T26	0	1	0	0
T33	2317	4	0	0
T38	1943	4	0	1
T39	0	34	0	1
T44	0	3	0	1
T46	0	4	0	0
T48	0	7	0	1
T53	16295	0	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T74	0	3	0	1
T75	0	0	0	1
T77	0	4	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	5649	0	117
T4	2661	0	0	0
T7	4704	15	0	1
T8	3235	0	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T33	2317	0	0	0
T37	0	3	0	1
T39	0	3	0	1
T47	0	31	0	1
T48	0	12	0	1
T49	0	4	0	1
T53	16295	0	0	0
T74	0	3	0	1
T75	0	26	0	1
T81	0	3	0	1
T82	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	3945	0	87
T4	2661	0	0	0
T7	4704	3	0	1
T8	3235	0	0	0
T10	0	37	0	1
T17	0	40	0	1
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T33	2317	4	0	1
T37	0	3	0	1
T41	0	26	0	1
T48	0	15	0	1
T53	16295	0	0	0
T75	0	3	0	1
T79	0	62	0	1
T83	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	597312	0	316
T1	609	235	0	0
T2	1954	1136	0	0
T3	2613	1123	0	2
T7	4704	337	0	0
T8	3235	1355	0	2
T11	0	0	0	2
T13	0	0	0	2
T18	1119	41	0	0
T19	1980	361	0	0
T20	1828	13	0	0
T21	2878	207	0	0
T22	1550	283	0	0
T52	0	0	0	2
T60	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	1250	0	81
T6	1781	0	0	0
T17	1789	10	0	1
T37	3355	3	0	1
T40	0	4	0	0
T41	0	3	0	1
T44	0	4	0	1
T46	1006	0	0	0
T50	0	3	0	1
T51	0	15	0	1
T52	0	4	0	0
T65	1812	0	0	0
T66	0	4	0	0
T69	3006	0	0	0
T70	6070	0	0	0
T71	1887	0	0	0
T72	1953	0	0	0
T79	0	0	0	1
T84	0	3	0	1
T85	2385	0	0	0
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	164543	0	0
T1	609	304	0	0
T2	1954	1152	0	0
T3	2613	0	0	0
T4	0	1152	0	0
T5	0	650	0	0
T6	0	364	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17434	0	0
T12	0	1127	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	644	0	0
T61	0	1137	0	0
T62	0	1165	0	0