Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	197815605	8845923	0	0
boot_gen_cmd_rd_A	197815605	58346	0	0
boot_ins_cmd_rd_A	197815605	65938	0	0
ctrl_rd_A	197815605	57680	0	0
err_code_test_rd_A	197815605	66570	0	0
intr_enable_rd_A	197815605	65103	0	0
max_num_reqs_between_reseeds_rd_A	197815605	59454	0	0
regwen_rd_A	197815605	67447	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	8845923	0	0
T34	280592	157824	0	0
T35	181247	77724	0	0
T36	0	167412	0	0
T95	2181	0	0	0
T102	0	154278	0	0
T114	3166	0	0	0
T216	2058	0	0	0
T220	0	449834	0	0
T221	0	229178	0	0
T222	0	22661	0	0
T223	0	79787	0	0
T224	0	404929	0	0
T225	0	61896	0	0
T226	1231	0	0	0
T227	1593	0	0	0
T228	1777	0	0	0
T229	1460	0	0	0
T230	2595	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	58346	0	0
T14	45168	0	0	0
T130	1567	0	0	0
T149	3061	0	0	0
T206	841	0	0	0
T224	117987	11671	0	0
T225	0	1891	0	0
T231	0	1699	0	0
T232	0	4999	0	0
T233	0	5480	0	0
T234	0	3283	0	0
T235	0	386	0	0
T236	0	4043	0	0
T237	0	4917	0	0
T238	0	3220	0	0
T239	1729	0	0	0
T240	23271	0	0	0
T241	1101	0	0	0
T242	2548	0	0	0
T243	1826	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	65938	0	0
T14	45168	0	0	0
T130	1567	0	0	0
T149	3061	0	0	0
T206	841	0	0	0
T224	117987	13028	0	0
T225	0	2061	0	0
T231	0	1963	0	0
T232	0	6081	0	0
T233	0	6188	0	0
T234	0	3435	0	0
T235	0	400	0	0
T236	0	4304	0	0
T237	0	5309	0	0
T238	0	3590	0	0
T239	1729	0	0	0
T240	23271	0	0	0
T241	1101	0	0	0
T242	2548	0	0	0
T243	1826	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	57680	0	0
T4	2661	0	0	0
T8	3235	0	0	0
T11	49473	0	0	0
T18	1119	6	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T33	2317	0	0	0
T53	16295	0	0	0
T100	0	4	0	0
T114	0	3	0	0
T139	0	4	0	0
T149	0	7	0	0
T224	0	11902	0	0
T225	0	1900	0	0
T240	0	5	0	0
T244	0	2	0	0
T245	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	66570	0	0
T14	45168	0	0	0
T130	1567	0	0	0
T149	3061	0	0	0
T206	841	0	0	0
T224	117987	12928	0	0
T225	0	2110	0	0
T231	0	2088	0	0
T232	0	5746	0	0
T233	0	6373	0	0
T234	0	3456	0	0
T235	0	435	0	0
T236	0	4772	0	0
T237	0	5283	0	0
T238	0	3720	0	0
T239	1729	0	0	0
T240	23271	0	0	0
T241	1101	0	0	0
T242	2548	0	0	0
T243	1826	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	65103	0	0
T5	2759	0	0	0
T11	49473	0	0	0
T12	2212	0	0	0
T15	2530	0	0	0
T38	1943	0	0	0
T53	16295	12	0	0
T54	5571	0	0	0
T60	1184	0	0	0
T61	2876	0	0	0
T62	2312	0	0	0
T224	0	11851	0	0
T225	0	2119	0	0
T231	0	1825	0	0
T232	0	6074	0	0
T240	0	123	0	0
T244	0	47	0	0
T246	0	36	0	0
T247	0	71	0	0
T248	0	63	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	59454	0	0
T14	45168	0	0	0
T130	1567	0	0	0
T149	3061	0	0	0
T206	841	0	0	0
T224	117987	11979	0	0
T225	0	1764	0	0
T231	0	1715	0	0
T232	0	4885	0	0
T233	0	5500	0	0
T234	0	3062	0	0
T235	0	362	0	0
T236	0	4031	0	0
T237	0	4640	0	0
T238	0	3330	0	0
T239	1729	0	0	0
T240	23271	0	0	0
T241	1101	0	0	0
T242	2548	0	0	0
T243	1826	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197815605	67447	0	0
T14	45168	0	0	0
T130	1567	0	0	0
T149	3061	0	0	0
T206	841	0	0	0
T224	117987	13094	0	0
T225	0	2186	0	0
T231	0	1875	0	0
T232	0	5416	0	0
T233	0	6534	0	0
T234	0	3711	0	0
T235	0	442	0	0
T236	0	4407	0	0
T237	0	5372	0	0
T238	0	3840	0	0
T239	1729	0	0	0
T240	23271	0	0	0
T241	1101	0	0	0
T242	2548	0	0	0
T243	1826	0	0	0