Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.07	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.18	99.92	92.75	82.84	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T4,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T39,T40	Yes	T2,T39,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T10,T41	Yes	T3,T10,T41	INPUT
edn_i[3].edn_req	Yes	Yes	T27,T41,T8	Yes	T27,T41,T8	INPUT
edn_i[4].edn_req	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T11,T44,T45	Yes	T11,T44,T45	INPUT
edn_i[6].edn_req	Yes	Yes	T23,T41,T46	Yes	T23,T41,T46	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T22	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T28	Yes	T1,T2,T22	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T39,T40	Yes	T2,T39,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T9,T47,T12	Yes	T9,T48,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T39,T40	Yes	T2,T39,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T10,T41,T40	Yes	T3,T10,T41	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T41,T40	Yes	T10,T41,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T10,T41	Yes	T3,T10,T41	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T41,T8,T40	Yes	T27,T41,T8	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T20,T49,T50	Yes	T41,T40,T20	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T27,T41,T40	Yes	T27,T41,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T43,T51,T12	Yes	T41,T43,T20	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T11,T44,T45	Yes	T11,T44,T45	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T11,T45,T41	Yes	T11,T44,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T11,T44,T45	Yes	T11,T44,T45	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T41,T46,T40	Yes	T41,T46,T40	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T46,T40	Yes	T41,T46,T40	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T23,T41,T46	Yes	T23,T41,T46	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T10,T11	Yes	T1,T3,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T3,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T52,T42	Yes	T2,T52,T42	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T53,T6	Yes	T4,T53,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T53,T6	Yes	T4,T53,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T54,T55,T36	Yes	T54,T55,T36	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T54,T15,T55	Yes	T54,T15,T55	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	207176215	207001638	0	0
CsrngAppIfOut_A	207176215	207001638	0	0
FpvSecCmCntAlertCheck_A	207176215	108	0	0
FpvSecCmGenCmdFifoRptrCheck_A	207176215	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	207176215	70	0	0
FpvSecCmMainFsmCheck_A	207176215	70	0	0
FpvSecCmRegWeOnehotCheck_A	207176215	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	207176215	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	207176215	70	0	0
IntrEdnCmdReqDoneKnownO_A	207176215	207001638	0	0
TlAReadyKnownO_A	207176215	207001638	0	0
TlDValidKnownO_A	207176215	207001638	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	207176215	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[0].EdnDataStable_A	207176215	22193	0	425
gen_edn_if_asserts[0].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[1].EdnDataStable_A	207176215	9614	0	148
gen_edn_if_asserts[1].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[2].EdnDataStable_A	207176215	5907	0	124
gen_edn_if_asserts[2].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[3].EdnDataStable_A	207176215	4139	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[4].EdnDataStable_A	207176215	2142	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[5].EdnDataStable_A	207176215	4326	0	88
gen_edn_if_asserts[5].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	207176215	141056	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	207176215	534996	0	318
gen_edn_if_asserts[6].EdnDataStable_A	207176215	5769	0	70
gen_edn_if_asserts[6].EdnEndPointOut_A	207176215	207001638	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	207176215	141056	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	108	0	0
T4	2259	1	0	0
T5	2861	0	0	0
T11	2459	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	10	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T44	1757	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	2212	0	0	0
T63	1771	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	70	0	0
T17	23925	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1268	0	0	0
T67	3048	0	0	0
T68	2865	0	0	0
T69	2671	0	0	0
T70	19587	0	0	0
T71	1639	0	0	0
T72	1628	0	0	0
T73	3237	0	0	0
T74	4047	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	22193	0	425
T1	3955	49	0	1
T2	2377	4	0	0
T3	2645	0	0	0
T4	2259	0	0	0
T5	2861	6	0	1
T10	3005	0	0	0
T11	2459	0	0	0
T22	1440	3	0	1
T23	950	0	0	0
T24	3119	3	0	1
T28	0	8	0	1
T52	0	4	0	1
T54	0	0	0	1
T62	0	9	0	1
T63	0	46	0	1
T81	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	9614	0	148
T2	2377	4	0	1
T3	2645	0	0	0
T4	2259	0	0	0
T5	2861	0	0	0
T10	3005	0	0	0
T11	2459	0	0	0
T12	0	15	0	1
T13	0	0	0	1
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T39	0	4	0	0
T40	0	3	0	1
T47	0	3	0	1
T48	0	4	0	1
T49	0	3	0	1
T50	0	45	0	1
T82	0	4	0	1
T83	0	15	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	5907	0	124
T3	2645	4	0	0
T4	2259	0	0	0
T5	2861	0	0	0
T10	3005	291	0	1
T11	2459	0	0	0
T13	0	18	0	1
T20	0	982	0	1
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T40	0	32	0	1
T41	0	25	0	1
T43	0	3	0	1
T44	1757	0	0	0
T49	0	39	0	1
T50	0	3	0	1
T84	0	15	0	1
T85	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	4139	0	107
T12	0	3	0	1
T13	0	15	0	1
T20	0	45	0	1
T27	1638	4	0	1
T28	1667	0	0	0
T39	1150	0	0	0
T40	0	3	0	1
T41	2529	19	0	1
T44	1757	0	0	0
T45	1698	0	0	0
T49	0	40	0	1
T50	0	19	0	1
T52	2552	0	0	0
T53	1148	0	0	0
T62	2212	0	0	0
T63	1771	0	0	0
T86	0	4	0	1
T87	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	2142	0	100
T6	490	0	0	0
T7	587	0	0	0
T8	1546	0	0	0
T12	0	13	0	1
T15	815	0	0	0
T20	0	20	0	1
T39	1150	0	0	0
T41	2529	3	0	1
T42	1521	4	0	1
T43	0	49	0	1
T46	1613	0	0	0
T49	0	11	0	1
T50	0	3	0	1
T51	0	1	0	0
T54	8835	0	0	0
T81	1670	0	0	0
T85	0	19	0	1
T87	0	0	0	1
T88	0	4	0	0
T89	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	4326	0	88
T11	2459	189	0	1
T13	0	25	0	1
T20	0	3	0	1
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	1	0	0
T41	2529	23	0	1
T44	1757	19	0	1
T45	1698	43	0	1
T49	0	3	0	1
T52	2552	0	0	0
T53	1148	0	0	0
T62	2212	0	0	0
T63	1771	0	0	0
T90	0	4	0	1
T91	0	3	0	1
T92	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	534996	0	318
T1	3955	36	0	0
T2	2377	342	0	0
T3	2645	1546	0	2
T4	2259	655	0	0
T5	2861	28	0	0
T10	3005	148	0	0
T11	2459	155	0	0
T22	1440	20	0	0
T23	950	57	0	0
T24	3119	52	0	0
T37	0	0	0	2
T38	0	0	0	2
T53	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	5769	0	70
T11	2459	0	0	0
T12	0	12	0	1
T13	0	28	0	1
T20	0	48	0	1
T23	950	3	0	1
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T32	0	1	0	0
T40	0	43	0	1
T41	0	40	0	1
T44	1757	0	0	0
T46	0	52	0	1
T49	0	3	0	1
T52	2552	0	0	0
T53	1148	0	0	0
T62	2212	0	0	0
T63	1771	0	0	0
T85	0	0	0	1
T87	0	0	0	1
T93	0	4	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	141056	0	0
T4	2259	657	0	0
T5	2861	0	0	0
T6	0	212	0	0
T7	0	212	0	0
T8	0	782	0	0
T9	0	608	0	0
T11	2459	0	0	0
T15	0	360	0	0
T16	0	416	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T31	0	19	0	0
T44	1757	0	0	0
T51	0	1109	0	0
T56	0	594	0	0
T62	2212	0	0	0
T63	1771	0	0	0