Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207644325	9536549	0	0
boot_gen_cmd_rd_A	207644325	56218	0	0
boot_ins_cmd_rd_A	207644325	64340	0	0
ctrl_rd_A	207644325	55678	0	0
err_code_test_rd_A	207644325	64385	0	0
intr_enable_rd_A	207644325	62197	0	0
max_num_reqs_between_reseeds_rd_A	207644325	56434	0	0
regwen_rd_A	207644325	65004	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	9536549	0	0
T9	1574	0	0	0
T20	7362	0	0	0
T31	1298	0	0	0
T36	247179	100668	0	0
T37	407498	228755	0	0
T38	0	349790	0	0
T51	2145	0	0	0
T75	1437	0	0	0
T76	1005	0	0	0
T91	1019	0	0	0
T227	0	250850	0	0
T228	0	104872	0	0
T229	0	140107	0	0
T230	0	235742	0	0
T231	0	231812	0	0
T232	0	56224	0	0
T233	0	89591	0	0
T234	999	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	56218	0	0
T12	1950	0	0	0
T38	100571	10153	0	0
T47	1331	0	0	0
T48	2643	0	0	0
T77	1237	0	0	0
T99	1791	0	0	0
T103	2591	0	0	0
T105	1951	0	0	0
T107	2472	0	0	0
T235	0	8170	0	0
T236	0	6212	0	0
T237	0	1918	0	0
T238	0	2253	0	0
T239	0	5382	0	0
T240	0	2641	0	0
T241	0	4508	0	0
T242	0	1892	0	0
T243	0	5783	0	0
T244	4699	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	64340	0	0
T12	1950	0	0	0
T38	100571	11255	0	0
T47	1331	0	0	0
T48	2643	0	0	0
T77	1237	0	0	0
T99	1791	0	0	0
T103	2591	0	0	0
T105	1951	0	0	0
T107	2472	0	0	0
T235	0	9829	0	0
T236	0	7305	0	0
T237	0	2154	0	0
T238	0	2696	0	0
T239	0	6100	0	0
T240	0	3308	0	0
T241	0	4796	0	0
T242	0	2436	0	0
T243	0	6201	0	0
T244	4699	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	55678	0	0
T20	7362	0	0	0
T31	1298	0	0	0
T36	247179	0	0	0
T38	0	9604	0	0
T40	2389	4	0	0
T43	2135	0	0	0
T51	2145	0	0	0
T55	17028	0	0	0
T75	1437	0	0	0
T76	1005	0	0	0
T90	2658	0	0	0
T120	0	6	0	0
T203	0	8	0	0
T235	0	8052	0	0
T236	0	6344	0	0
T237	0	1653	0	0
T245	0	3	0	0
T246	0	1	0	0
T247	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	64385	0	0
T12	1950	0	0	0
T38	100571	11746	0	0
T47	1331	0	0	0
T48	2643	0	0	0
T77	1237	0	0	0
T99	1791	0	0	0
T103	2591	0	0	0
T105	1951	0	0	0
T107	2472	0	0	0
T235	0	9032	0	0
T236	0	7193	0	0
T237	0	2165	0	0
T238	0	2540	0	0
T239	0	5994	0	0
T240	0	3107	0	0
T241	0	5124	0	0
T242	0	2423	0	0
T243	0	6666	0	0
T244	4699	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	62197	0	0
T15	815	0	0	0
T20	7362	0	0	0
T36	247179	0	0	0
T38	0	10875	0	0
T40	2389	0	0	0
T42	1521	0	0	0
T43	2135	0	0	0
T46	1613	0	0	0
T54	8835	18	0	0
T55	17028	0	0	0
T90	2658	0	0	0
T235	0	8764	0	0
T236	0	6597	0	0
T237	0	1953	0	0
T238	0	3061	0	0
T239	0	5817	0	0
T248	0	15	0	0
T249	0	62	0	0
T250	0	73	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	56434	0	0
T12	1950	0	0	0
T38	100571	9795	0	0
T47	1331	0	0	0
T48	2643	0	0	0
T77	1237	0	0	0
T99	1791	0	0	0
T103	2591	0	0	0
T105	1951	0	0	0
T107	2472	0	0	0
T235	0	8139	0	0
T236	0	6154	0	0
T237	0	1787	0	0
T238	0	2182	0	0
T239	0	5265	0	0
T240	0	2831	0	0
T241	0	4339	0	0
T242	0	1940	0	0
T243	0	5801	0	0
T244	4699	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644325	65004	0	0
T12	1950	0	0	0
T38	100571	11780	0	0
T47	1331	0	0	0
T48	2643	0	0	0
T77	1237	0	0	0
T99	1791	0	0	0
T103	2591	0	0	0
T105	1951	0	0	0
T107	2472	0	0	0
T235	0	9299	0	0
T236	0	6828	0	0
T237	0	2028	0	0
T238	0	2885	0	0
T239	0	6035	0	0
T240	0	3336	0	0
T241	0	5125	0	0
T242	0	2205	0	0
T243	0	6484	0	0
T244	4699	0	0	0