Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.01	98.25	93.91	97.07	90.70	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.97	99.92	92.66	82.84	90.70	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T4,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T35,T36	Yes	T5,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T37,T38	Yes	T23,T37,T38	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T23,T28	Yes	T1,T23,T28	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T14,T39	Yes	T1,T14,T39	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T40,T41	Yes	T1,T40,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T29,T10	Yes	T1,T29,T10	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T5,T23	Yes	T3,T5,T23	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T5,T6,T9	Yes	T5,T23,T6	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T37,T10	Yes	T23,T37,T10	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T23,T10,T42	Yes	T23,T37,T10	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T37,T10	Yes	T23,T37,T10	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T28,T21	Yes	T1,T23,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T43,T44	Yes	T1,T23,T28	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T23,T28	Yes	T1,T23,T28	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T23,T45	Yes	T1,T23,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T39,T13	Yes	T1,T39,T13	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T13,T43,T46	Yes	T39,T13,T47	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T39,T13	Yes	T1,T39,T13	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T41,T48	Yes	T1,T41,T48	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T49,T43,T50	Yes	T40,T41,T51	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T40,T41	Yes	T1,T40,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T29,T10,T52	Yes	T1,T29,T10	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T10,T53,T54	Yes	T1,T10,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T29,T10	Yes	T1,T29,T10	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T5,T23	Yes	T1,T5,T23	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T5,T23	Yes	T1,T5,T23	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T39,T55	Yes	T2,T39,T55	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T5,T35	Yes	T3,T5,T35	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T35	Yes	T4,T5,T35	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217284529	217084686	0	0
CsrngAppIfOut_A	217284529	217084686	0	0
FpvSecCmCntAlertCheck_A	217284529	136	0	0
FpvSecCmGenCmdFifoRptrCheck_A	217284529	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	217284529	90	0	0
FpvSecCmMainFsmCheck_A	217284529	90	0	0
FpvSecCmRegWeOnehotCheck_A	217284529	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	217284529	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	217284529	90	0	0
IntrEdnCmdReqDoneKnownO_A	217284529	217084686	0	0
TlAReadyKnownO_A	217284529	217084686	0	0
TlDValidKnownO_A	217284529	217084686	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217284529	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[0].EdnDataStable_A	217284529	28241	0	437
gen_edn_if_asserts[0].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[1].EdnDataStable_A	217284529	3290	0	142
gen_edn_if_asserts[1].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[2].EdnDataStable_A	217284529	51343	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[3].EdnDataStable_A	217284529	10045	0	120
gen_edn_if_asserts[3].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[4].EdnDataStable_A	217284529	3565	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[5].EdnDataStable_A	217284529	2193	0	107
gen_edn_if_asserts[5].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217284529	173759	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217284529	586000	0	306
gen_edn_if_asserts[6].EdnDataStable_A	217284529	2908	0	93
gen_edn_if_asserts[6].EdnEndPointOut_A	217284529	217084686	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217284529	173759	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	136	0	0
T7	631	1	0	0
T8	0	1	0	0
T9	5599	0	0	0
T14	1813	1	0	0
T15	795	1	0	0
T16	24709	10	0	0
T17	0	20	0	0
T27	1969	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T45	2423	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	25378	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	90	0	0
T13	2982	0	0	0
T16	24709	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T21	2069	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T39	1546	0	0	0
T45	2423	0	0	0
T60	25378	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	15893	0	0	0
T64	1091	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	28241	0	437
T3	2814	3	0	0
T4	741	1	0	0
T5	190600	45	0	0
T6	2418	0	0	0
T7	631	0	0	0
T9	5599	687	0	1
T14	1813	0	0	0
T15	795	0	0	0
T19	0	0	0	1
T23	2398	3	0	1
T24	0	0	0	1
T27	1969	4	0	1
T35	0	71	0	1
T45	0	4	0	1
T55	0	0	0	1
T60	0	15	0	0
T63	0	13	0	0
T66	0	0	0	1
T67	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	3290	0	142
T6	2418	0	0	0
T7	631	0	0	0
T9	5599	0	0	0
T10	0	31	0	1
T14	1813	0	0	0
T15	795	0	0	0
T16	24709	0	0	0
T23	2398	33	0	1
T27	1969	0	0	0
T28	2247	0	0	0
T35	282048	0	0	0
T37	0	7	0	1
T42	0	17	0	1
T43	0	3	0	1
T69	0	4	0	1
T70	0	33	0	1
T71	0	3	0	1
T72	0	1	0	0
T73	0	3	0	1
T74	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	51343	0	129
T1	2131	44	0	1
T2	1851	0	0	0
T3	2814	0	0	0
T4	741	0	0	0
T5	190600	0	0	0
T6	2418	0	0	0
T7	631	0	0	0
T14	1813	0	0	0
T15	795	0	0	0
T21	0	3	0	1
T23	2398	3	0	1
T28	0	4	0	1
T42	0	3	0	1
T43	0	29	0	1
T49	0	4	0	1
T70	0	3	0	1
T75	0	1	0	0
T76	0	4	0	1
T77	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	10045	0	120
T1	2131	44	0	1
T2	1851	4	0	1
T3	2814	0	0	0
T4	741	0	0	0
T5	190600	0	0	0
T6	2418	0	0	0
T7	631	0	0	0
T10	0	11	0	1
T14	1813	0	0	0
T15	795	0	0	0
T21	0	41	0	1
T22	0	1131	0	1
T23	2398	39	0	1
T40	0	4	0	0
T43	0	0	0	1
T45	0	4	0	0
T51	0	1061	0	1
T70	0	3	0	1
T78	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	3565	0	104
T1	2131	3	0	1
T2	1851	0	0	0
T3	2814	0	0	0
T4	741	0	0	0
T5	190600	0	0	0
T6	2418	0	0	0
T7	631	0	0	0
T13	0	80	0	1
T14	1813	0	0	0
T15	795	0	0	0
T20	0	4	0	0
T23	2398	0	0	0
T39	0	4	0	1
T43	0	27	0	1
T44	0	0	0	1
T46	0	5	0	1
T47	0	4	0	1
T70	0	3	0	1
T77	0	3	0	1
T79	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	2193	0	107
T1	2131	3	0	1
T2	1851	0	0	0
T3	2814	0	0	0
T4	741	0	0	0
T5	190600	0	0	0
T6	2418	0	0	0
T7	631	0	0	0
T14	1813	0	0	0
T15	795	0	0	0
T23	2398	0	0	0
T40	0	1	0	0
T41	0	4	0	0
T43	0	41	0	1
T44	0	0	0	1
T46	0	0	0	1
T48	0	3	0	1
T49	0	4	0	0
T50	0	12	0	1
T51	0	3	0	1
T70	0	3	0	1
T79	0	3	0	1
T80	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	586000	0	306
T1	2131	14	0	0
T2	1851	131	0	0
T3	2814	1764	0	2
T4	741	228	0	0
T5	190600	1806	0	2
T6	2418	1454	0	0
T7	631	310	0	0
T14	1813	1042	0	0
T15	795	367	0	0
T16	0	0	0	2
T20	0	0	0	2
T23	2398	49	0	0
T36	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	2908	0	93
T1	2131	3	0	1
T2	1851	0	0	0
T3	2814	0	0	0
T4	741	0	0	0
T5	190600	0	0	0
T6	2418	0	0	0
T7	631	0	0	0
T10	0	49	0	1
T14	1813	0	0	0
T15	795	0	0	0
T23	2398	0	0	0
T29	0	1	0	0
T43	0	3	0	1
T46	0	10	0	1
T52	0	4	0	0
T53	0	1	0	0
T54	0	0	0	1
T70	0	3	0	1
T77	0	3	0	1
T80	0	3	0	1
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	173759	0	0
T4	741	310	0	0
T5	190600	0	0	0
T6	2418	1124	0	0
T7	631	264	0	0
T8	0	1104	0	0
T9	5599	0	0	0
T14	1813	1044	0	0
T15	795	408	0	0
T16	24709	9242	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T29	0	19	0	0
T38	0	362	0	0
T68	0	1112	0	0