Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217787580	9718105	0	0
boot_gen_cmd_rd_A	217787580	59490	0	0
boot_ins_cmd_rd_A	217787580	66415	0	0
ctrl_rd_A	217787580	58510	0	0
err_code_test_rd_A	217787580	65804	0	0
intr_enable_rd_A	217787580	65576	0	0
max_num_reqs_between_reseeds_rd_A	217787580	59605	0	0
regwen_rd_A	217787580	68152	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	9718105	0	0
T5	190600	77913	0	0
T6	2418	0	0	0
T7	631	0	0	0
T9	5599	0	0	0
T14	1813	0	0	0
T15	795	0	0	0
T16	24709	0	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T35	282048	162659	0	0
T36	0	260773	0	0
T86	0	153661	0	0
T87	0	42201	0	0
T212	0	314673	0	0
T213	0	117600	0	0
T214	0	113965	0	0
T215	0	108675	0	0
T216	0	118401	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	59490	0	0
T17	52921	0	0	0
T50	3101	0	0	0
T87	0	665	0	0
T91	2002	0	0	0
T124	2498	0	0	0
T164	2183	0	0	0
T212	902417	9071	0	0
T217	0	7511	0	0
T218	0	11194	0	0
T219	0	2227	0	0
T220	0	1703	0	0
T221	0	1892	0	0
T222	0	2567	0	0
T223	0	1884	0	0
T224	0	1780	0	0
T225	3682	0	0	0
T226	1753	0	0	0
T227	2117	0	0	0
T228	1138	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	66415	0	0
T17	52921	0	0	0
T50	3101	0	0	0
T87	0	733	0	0
T91	2002	0	0	0
T124	2498	0	0	0
T164	2183	0	0	0
T212	902417	10424	0	0
T217	0	8239	0	0
T218	0	12639	0	0
T219	0	2322	0	0
T220	0	2189	0	0
T221	0	2066	0	0
T222	0	2981	0	0
T223	0	1987	0	0
T224	0	1994	0	0
T225	3682	0	0	0
T226	1753	0	0	0
T227	2117	0	0	0
T228	1138	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	58510	0	0
T20	3461	0	0	0
T24	1661	0	0	0
T36	456696	0	0	0
T37	3357	0	0	0
T38	713	0	0	0
T40	2676	0	0	0
T55	2450	8	0	0
T67	2952	0	0	0
T68	1911	0	0	0
T77	0	6	0	0
T87	0	553	0	0
T88	1670	0	0	0
T212	0	9353	0	0
T217	0	7314	0	0
T218	0	10634	0	0
T219	0	2271	0	0
T220	0	1884	0	0
T229	0	1	0	0
T230	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	65804	0	0
T17	52921	0	0	0
T50	3101	0	0	0
T87	0	778	0	0
T91	2002	0	0	0
T124	2498	0	0	0
T164	2183	0	0	0
T212	902417	10475	0	0
T217	0	8227	0	0
T218	0	11823	0	0
T219	0	2642	0	0
T220	0	2120	0	0
T221	0	1981	0	0
T222	0	2992	0	0
T223	0	2001	0	0
T224	0	1936	0	0
T225	3682	0	0	0
T226	1753	0	0	0
T227	2117	0	0	0
T228	1138	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	65576	0	0
T8	1999	0	0	0
T19	3043	0	0	0
T20	3461	0	0	0
T21	2069	0	0	0
T24	1661	0	0	0
T55	2450	0	0	0
T63	15893	32	0	0
T64	1091	0	0	0
T66	1677	0	0	0
T67	2952	0	0	0
T87	0	798	0	0
T212	0	9636	0	0
T217	0	7676	0	0
T218	0	11598	0	0
T219	0	2449	0	0
T220	0	2218	0	0
T221	0	2539	0	0
T231	0	5	0	0
T232	0	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	59605	0	0
T17	52921	0	0	0
T50	3101	0	0	0
T87	0	699	0	0
T91	2002	0	0	0
T124	2498	0	0	0
T164	2183	0	0	0
T212	902417	9100	0	0
T217	0	7234	0	0
T218	0	11365	0	0
T219	0	2044	0	0
T220	0	1953	0	0
T221	0	1751	0	0
T222	0	2585	0	0
T223	0	1900	0	0
T224	0	1597	0	0
T225	3682	0	0	0
T226	1753	0	0	0
T227	2117	0	0	0
T228	1138	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217787580	68152	0	0
T17	52921	0	0	0
T50	3101	0	0	0
T87	0	826	0	0
T91	2002	0	0	0
T124	2498	0	0	0
T164	2183	0	0	0
T212	902417	10599	0	0
T217	0	8276	0	0
T218	0	12121	0	0
T219	0	2506	0	0
T220	0	2031	0	0
T221	0	2002	0	0
T222	0	3292	0	0
T223	0	2038	0	0
T224	0	1907	0	0
T225	3682	0	0	0
T226	1753	0	0	0
T227	2117	0	0	0
T228	1138	0	0	0