Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T49,T62
1	1	Covered	T3,T18,T19

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T23,T11
1	1	Covered	T2,T18,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T27
1	0	Covered	T5,T6,T15

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T27
1	Covered	T5,T6,T15

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T27
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T27
1	Covered	T5,T6,T15

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T19,T27

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T10,T11
AutoCaptGenCnt	143	Covered	T2,T10,T11
AutoCaptReseedCnt	141	Covered	T2,T10,T11
AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns	69	Covered	T2,T18,T10
AutoSendGenCmd	150	Covered	T2,T10,T11
AutoSendReseedCmd	162	Covered	T2,T10,T11
BootDone	98	Covered	T3,T19,T27
BootGenAckWait	90	Covered	T3,T19,T27
BootInsAckWait	80	Covered	T3,T18,T19
BootLoadGen	85	Covered	T3,T18,T19
BootLoadIns	65	Covered	T3,T18,T19
BootLoadUni	102	Covered	T3,T19,T27
BootPulse	94	Covered	T3,T19,T27
BootUniAckWait	107	Covered	T3,T27,T32
Error	188	Covered	T5,T6,T15
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T18,T19,T27
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T11
AutoAckWait->Error	188	Covered	T123,T124
AutoAckWait->Idle	211	Covered	T11,T24,T44
AutoAckWait->RejectCsrngEntropy	188	Covered	T90,T106,T108
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T10,T11
AutoCaptGenCnt->Error	188	Covered	T57,T125,T126
AutoCaptGenCnt->Idle	211	Covered	T47,T127,T128
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T66,T129,T130
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T10,T11
AutoCaptReseedCnt->Error	188	Covered	T131
AutoCaptReseedCnt->Idle	211	Covered	T11,T132,T133
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T134,T135,T136
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T10,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T11
AutoDispatch->Error	188	Covered	T137,T138,T139
AutoDispatch->Idle	138	Covered	T2,T10,T25
AutoDispatch->RejectCsrngEntropy	188	Covered	T76,T140,T141
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait->Error	188	Covered	T142
AutoFirstAckWait->Idle	211	Covered	T143,T144,T145
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T51,T146,T147
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns->Error	188	Covered	T148,T149,T150
AutoLoadIns->Idle	211	Covered	T18,T24,T107
AutoLoadIns->RejectCsrngEntropy	188	Covered	T77,T109,T151
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T10,T11
AutoSendGenCmd->Error	188	Covered	T152,T153
AutoSendGenCmd->Idle	211	Covered	T154,T155,T156
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T157,T158,T159
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T10,T11
AutoSendReseedCmd->Error	188	Covered	T113,T160,T161
AutoSendReseedCmd->Idle	211	Covered	T44,T162,T163
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T114,T164,T165
BootDone->BootLoadUni	102	Covered	T3,T19,T27
BootDone->Error	188	Covered	T16,T166,T167
BootDone->Idle	211	Covered	T168,T169,T170
BootDone->RejectCsrngEntropy	188	Covered	T23,T79,T171
BootGenAckWait->BootPulse	94	Covered	T3,T19,T27
BootGenAckWait->Error	188	Covered	T172
BootGenAckWait->Idle	211	Covered	T62,T173,T174
BootGenAckWait->RejectCsrngEntropy	188	Covered	T115,T175,T176
BootInsAckWait->BootLoadGen	85	Covered	T3,T18,T19
BootInsAckWait->Error	188	Covered	T17,T59,T177
BootInsAckWait->Idle	211	Covered	T15,T16,T17
BootInsAckWait->RejectCsrngEntropy	188	Covered	T85,T178,T179
BootLoadGen->BootGenAckWait	90	Covered	T3,T19,T27
BootLoadGen->Error	188	Covered	T180,T181,T182
BootLoadGen->Idle	211	Covered	T81,T84,T183
BootLoadGen->RejectCsrngEntropy	188	Covered	T18,T27,T91
BootLoadIns->BootInsAckWait	80	Covered	T3,T18,T19
BootLoadIns->Error	188	Covered	T15,T184,T185
BootLoadIns->Idle	211	Covered	T92,T87,T94
BootLoadIns->RejectCsrngEntropy	188	Covered	T186,T187,T188
BootLoadUni->BootUniAckWait	107	Covered	T3,T27,T32
BootLoadUni->Error	188	Covered	T189,T190
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T19,T122,T107
BootPulse->BootDone	98	Covered	T3,T19,T27
BootPulse->Error	188	Covered	T174,T191,T192
BootPulse->Idle	211	Covered	T49,T193,T194
BootPulse->RejectCsrngEntropy	188	Covered	T70,T195,T196
BootUniAckWait->Error	188	Covered	T197,T198,T199
BootUniAckWait->Idle	112	Covered	T3,T27,T32
BootUniAckWait->RejectCsrngEntropy	188	Covered	T32,T50,T116
Idle->AutoLoadIns	69	Covered	T2,T18,T10
Idle->BootLoadIns	65	Covered	T3,T18,T19
Idle->Error	188	Covered	T20,T21,T22
Idle->RejectCsrngEntropy	188	Covered	T18,T27,T32
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T200,T201,T202
RejectCsrngEntropy->Idle	211	Covered	T18,T19,T27
SWPortMode->Error	188	Covered	T5,T6,T53
SWPortMode->Idle	211	Covered	T19,T23,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T19,T23,T76

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T27
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T19,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T27,T23,T32
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T32,T50
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T27,T32
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T18,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T10,T25
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T27
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T62,T74,T7

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T15
1	0	1	-	Not Covered
1	0	0	-	Covered	T18,T19,T27
0	-	-	1	Covered	T18,T19,T27
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	216839667	137934	0	0
FpvSecCmErrorStEscalate_A	216839667	138972	0	0
u_state_regs_A	216799513	216620088	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	137934	0	0
T5	1368	629	0	0
T6	821	414	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	212	0	0
T16	0	1143	0	0
T17	0	324	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1108	0	0
T49	984	0	0	0
T53	0	1109	0	0
T60	1162	0	0	0
T62	0	1092	0	0
T74	0	1048	0	0
T75	0	468	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	138972	0	0
T5	1368	630	0	0
T6	821	415	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	213	0	0
T16	0	1144	0	0
T17	0	325	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1109	0	0
T49	984	0	0	0
T53	0	1110	0	0
T60	1162	0	0	0
T62	0	1093	0	0
T74	0	1049	0	0
T75	0	469	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216799513	216620088	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1221	1057	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0