| | | | | | | |
edn_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_alert_tx[1].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_edn_core |
94.21 |
99.92 |
92.66 |
82.54 |
92.44 |
98.83 |
98.88 |
gen_ep_blk[0].u_edn_ack_sm_ep |
97.14 |
100.00 |
100.00 |
|
85.71 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[0].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[1].u_edn_ack_sm_ep |
97.14 |
100.00 |
100.00 |
|
85.71 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[1].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[2].u_edn_ack_sm_ep |
97.14 |
100.00 |
100.00 |
|
85.71 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[2].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[3].u_edn_ack_sm_ep |
98.57 |
100.00 |
100.00 |
|
92.86 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[3].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[4].u_edn_ack_sm_ep |
97.14 |
100.00 |
100.00 |
|
85.71 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[4].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[5].u_edn_ack_sm_ep |
97.14 |
100.00 |
100.00 |
|
85.71 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[5].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
gen_ep_blk[6].u_edn_ack_sm_ep |
98.57 |
100.00 |
100.00 |
|
92.86 |
100.00 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_ep_blk[6].u_prim_packer_fifo_ep |
98.81 |
100.00 |
95.24 |
|
|
100.00 |
100.00 |
u_edn_main_sm |
98.16 |
100.00 |
94.44 |
|
98.65 |
97.73 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_intr_hw_edn_cmd_req_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_intr_hw_edn_fatal_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_arbiter_ppc_packer_arb |
95.16 |
95.00 |
92.31 |
|
|
100.00 |
93.33 |
u_prim_count_max_reqs_cntr |
70.79 |
|
|
70.79 |
|
|
|
u_prim_edge_detector_recov_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prim_fifo_sync_gencmd |
97.84 |
100.00 |
89.19 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_prim_fifo_sync_rescmd |
98.38 |
100.00 |
91.89 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sync_auto_req_mode |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_mubi4_sync_boot_req_mode |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_mubi4_sync_cmd_fifo_rst |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_mubi4_sync_edn_enable |
100.00 |
100.00 |
|
|
|
|
100.00 |
subtree... |
|
|
|
|
|
|
|
u_prim_packer_fifo_cs |
95.24 |
100.00 |
95.24 |
|
|
85.71 |
100.00 |
u_edn_cov_if |
25.00 |
50.00 |
0.00 |
|
|
|
|
u_reg |
96.95 |
95.02 |
97.57 |
100.00 |
|
92.16 |
100.00 |
u_alert_test_fatal_alert |
100.00 |
100.00 |
|
|
|
|
|
u_alert_test_recov_alert |
100.00 |
100.00 |
|
|
|
|
|
u_boot_gen_cmd |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_boot_ins_cmd |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
u_chk |
100.00 |
|
|
100.00 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_ctrl_auto_req_mode |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_boot_req_mode |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_cmd_fifo_rst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_edn_enable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_err_code_edn_ack_sm_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_edn_cntr_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_edn_main_sm_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_fifo_read_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_fifo_state_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_fifo_write_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_sfifo_gencmd_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_sfifo_rescmd_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_test |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_err_code_test0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_generate_cmd |
100.00 |
100.00 |
|
|
|
|
|
u_hw_cmd_sts_auto_mode |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_hw_cmd_sts_boot_mode |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_hw_cmd_sts_cmd_ack |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_hw_cmd_sts_cmd_sts |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_hw_cmd_sts_cmd_type |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_enable_edn_cmd_req_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_edn_fatal_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_state_edn_cmd_req_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_edn_fatal_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_test_edn_cmd_req_done |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_edn_fatal_err |
100.00 |
100.00 |
|
|
|
|
|
u_main_sm_state |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_max_num_reqs_between_reseeds |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_max_num_reqs_between_reseeds0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
u_recov_alert_sts_auto_req_mode_field_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_recov_alert_sts_boot_req_mode_field_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_recov_alert_sts_cmd_fifo_rst_field_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_recov_alert_sts_csrng_ack_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_recov_alert_sts_edn_bus_cmp_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_recov_alert_sts_edn_enable_field_alert |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reseed_cmd |
100.00 |
100.00 |
|
|
|
|
|
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_sw_cmd_req |
100.00 |
100.00 |
|
|
|
|
|
u_sw_cmd_sts_cmd_ack |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_sw_cmd_sts_cmd_rdy |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_sw_cmd_sts_cmd_reg_rdy |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_sw_cmd_sts_cmd_sts |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|