Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T97,T98
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T38,T39
1	0	1	Covered	T2,T18,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432990154	566875	0	0
DepthKnown_A	433679334	433320484	0	0
RvalidKnown_A	433679334	433320484	0	0
WreadyKnown_A	433679334	433320484	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	433356410	659601	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432990154	566875	0	0
T2	14922	8429	0	0
T3	5930	0	0	0
T4	901718	0	0	0
T5	722	0	0	0
T10	0	6588	0	0
T11	0	3557	0	0
T18	3676	75	0	0
T19	5118	449	0	0
T23	5422	252	0	0
T24	0	2714	0	0
T25	0	7069	0	0
T27	4050	0	0	0
T28	1708	0	0	0
T32	4726	0	0	0
T44	0	4299	0	0
T51	0	360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433679334	433320484	0	0
T1	10540	10438	0	0
T2	14922	14724	0	0
T3	5930	5790	0	0
T4	901718	901690	0	0
T5	2736	2408	0	0
T18	3676	3550	0	0
T19	5118	4950	0	0
T23	5422	5226	0	0
T27	4050	3906	0	0
T28	1708	1590	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433679334	433320484	0	0
T1	10540	10438	0	0
T2	14922	14724	0	0
T3	5930	5790	0	0
T4	901718	901690	0	0
T5	2736	2408	0	0
T18	3676	3550	0	0
T19	5118	4950	0	0
T23	5422	5226	0	0
T27	4050	3906	0	0
T28	1708	1590	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433679334	433320484	0	0
T1	10540	10438	0	0
T2	14922	14724	0	0
T3	5930	5790	0	0
T4	901718	901690	0	0
T5	2736	2408	0	0
T18	3676	3550	0	0
T19	5118	4950	0	0
T23	5422	5226	0	0
T27	4050	3906	0	0
T28	1708	1590	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	433356410	659601	0	0
T2	14922	8429	0	0
T3	5930	0	0	0
T4	901718	0	0	0
T5	2736	0	0	0
T6	0	306	0	0
T10	0	6588	0	0
T11	0	3557	0	0
T15	0	220	0	0
T18	3676	75	0	0
T19	5118	449	0	0
T23	5422	252	0	0
T24	0	2714	0	0
T27	4050	0	0	0
T28	1708	0	0	0
T32	4726	0	0	0
T51	0	360	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T38,T99
1	0	1	Covered	T2,T18,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216495077	289607	0	0
DepthKnown_A	216839667	216660242	0	0
RvalidKnown_A	216839667	216660242	0	0
WreadyKnown_A	216839667	216660242	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216678205	336263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216495077	289607	0	0
T2	7461	4239	0	0
T3	2965	0	0	0
T4	450859	0	0	0
T5	361	0	0	0
T10	0	3338	0	0
T11	0	1860	0	0
T18	1838	38	0	0
T19	2559	265	0	0
T23	2711	138	0	0
T24	0	1368	0	0
T25	0	3540	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T44	0	2173	0	0
T51	0	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216678205	336263	0	0
T2	7461	4239	0	0
T3	2965	0	0	0
T4	450859	0	0	0
T5	1368	0	0	0
T6	0	146	0	0
T10	0	3338	0	0
T11	0	1860	0	0
T15	0	109	0	0
T18	1838	38	0	0
T19	2559	265	0	0
T23	2711	138	0	0
T24	0	1368	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T51	0	179	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T23,T100
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T97,T98
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T101
1	0	1	Covered	T2,T18,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216495077	277268	0	0
DepthKnown_A	216839667	216660242	0	0
RvalidKnown_A	216839667	216660242	0	0
WreadyKnown_A	216839667	216660242	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216678205	323338	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216495077	277268	0	0
T2	7461	4190	0	0
T3	2965	0	0	0
T4	450859	0	0	0
T5	361	0	0	0
T10	0	3250	0	0
T11	0	1697	0	0
T18	1838	37	0	0
T19	2559	184	0	0
T23	2711	114	0	0
T24	0	1346	0	0
T25	0	3529	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T44	0	2126	0	0
T51	0	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216678205	323338	0	0
T2	7461	4190	0	0
T3	2965	0	0	0
T4	450859	0	0	0
T5	1368	0	0	0
T6	0	160	0	0
T10	0	3250	0	0
T11	0	1697	0	0
T15	0	111	0	0
T18	1838	37	0	0
T19	2559	184	0	0
T23	2711	114	0	0
T24	0	1346	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T51	0	181	0	0