Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	98.25	93.91	97.02	93.60	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.41	99.92	92.66	82.54	93.60	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T36,T14,T37

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T41,T42	Yes	T4,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T26,T13,T22	Yes	T26,T13,T22	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	INPUT
edn_i[3].edn_req	Yes	Yes	T26,T21,T43	Yes	T26,T21,T43	INPUT
edn_i[4].edn_req	Yes	Yes	T26,T23,T44	Yes	T26,T23,T44	INPUT
edn_i[5].edn_req	Yes	Yes	T13,T36,T45	Yes	T13,T36,T45	INPUT
edn_i[6].edn_req	Yes	Yes	T13,T44,T45	Yes	T13,T44,T45	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T27	Yes	T1,T2,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T5,T22	Yes	T4,T5,T46	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T13,T22,T43	Yes	T26,T13,T22	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T13,T22,T47	Yes	T26,T13,T22	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T13,T22	Yes	T26,T13,T22	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T25,T48,T49	Yes	T25,T23,T50	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T26,T21,T43	Yes	T26,T21,T43	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T26,T51,T48	Yes	T26,T21,T43	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T26,T21,T43	Yes	T26,T21,T43	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T26,T23,T44	Yes	T26,T23,T44	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T26,T23,T44	Yes	T26,T23,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T26,T23,T44	Yes	T26,T23,T44	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T13,T36,T45	Yes	T13,T36,T45	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T36,T52,T10	Yes	T36,T45,T53	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T13,T36,T45	Yes	T13,T36,T45	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T13,T44,T45	Yes	T13,T44,T45	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T13,T54,T55	Yes	T13,T45,T54	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T13,T44,T45	Yes	T13,T44,T45	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T4,T26	Yes	T1,T4,T26	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T4,T26	Yes	T4,T26,T13	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T1,T23,T56	Yes	T1,T23,T56	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T36,T14,T37	Yes	T36,T14,T37	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T36,T14,T37	Yes	T36,T14,T37	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	223938423	223742959	0	0
CsrngAppIfOut_A	223938423	223742959	0	0
FpvSecCmCntAlertCheck_A	223938423	133	0	0
FpvSecCmGenCmdFifoRptrCheck_A	223938423	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	223938423	90	0	0
FpvSecCmMainFsmCheck_A	223938423	90	0	0
FpvSecCmRegWeOnehotCheck_A	223938423	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	223938423	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	223938423	90	0	0
IntrEdnCmdReqDoneKnownO_A	223938423	223742959	0	0
TlAReadyKnownO_A	223938423	223742959	0	0
TlDValidKnownO_A	223938423	223742959	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	223938423	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[0].EdnDataStable_A	223938423	74742	0	415
gen_edn_if_asserts[0].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[1].EdnDataStable_A	223938423	6858	0	131
gen_edn_if_asserts[1].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[2].EdnDataStable_A	223938423	4372	0	117
gen_edn_if_asserts[2].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[3].EdnDataStable_A	223938423	1766	0	113
gen_edn_if_asserts[3].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[4].EdnDataStable_A	223938423	3001	0	88
gen_edn_if_asserts[4].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[5].EdnDataStable_A	223938423	3599	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	223938423	153754	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	223938423	573673	0	314
gen_edn_if_asserts[6].EdnDataStable_A	223938423	2759	0	72
gen_edn_if_asserts[6].EdnEndPointOut_A	223938423	223742959	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	223938423	153754	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	133	0	0
T8	0	1	0	0
T14	1696	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	20	0	0
T24	3710	0	0	0
T31	2439	0	0	0
T37	643	0	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T44	1869	0	0	0
T47	2069	0	0	0
T51	5459	0	0	0
T56	1755	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	90	0	0
T18	54323	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T48	2323	0	0	0
T49	2903	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	2391	0	0	0
T65	4558	0	0	0
T66	1347	0	0	0
T67	2986	0	0	0
T68	1761	0	0	0
T69	940	0	0	0
T70	4279	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	74742	0	415
T1	2845	8	0	1
T2	2811	4	0	1
T3	2896	0	0	0
T4	636609	17	0	0
T5	0	6	0	1
T13	2695	0	0	0
T17	1773	0	0	0
T22	0	15	0	1
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	15	0	1
T31	0	0	0	1
T41	0	88	0	0
T43	0	35	0	1
T46	0	4	0	1
T51	0	0	0	1
T73	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	6858	0	131
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	57	0	1
T21	3193	0	0	0
T22	0	31	0	1
T23	2573	0	0	0
T24	0	4	0	0
T26	2735	5	0	1
T27	1501	0	0	0
T36	2168	0	0	0
T43	0	7	0	1
T46	2279	0	0	0
T47	0	49	0	1
T49	0	0	0	1
T51	0	687	0	1
T56	0	4	0	1
T73	1736	0	0	0
T76	0	4	0	1
T77	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	4372	0	117
T3	2896	4	0	1
T4	636609	0	0	0
T5	12980	0	0	0
T13	2695	0	0	0
T17	1773	4	0	1
T21	3193	0	0	0
T22	0	3	0	1
T23	2573	4	0	1
T25	817	4	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T43	0	3	0	1
T48	0	44	0	1
T49	0	38	0	1
T50	0	3	0	1
T68	0	4	0	1
T70	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	1766	0	113
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	4	0	0
T23	2573	0	0	0
T26	2735	49	0	1
T27	1501	0	0	0
T36	2168	0	0	0
T37	0	1	0	0
T43	0	7	0	1
T46	2279	0	0	0
T48	0	19	0	1
T50	0	5	0	1
T51	0	19	0	1
T55	0	3	0	1
T70	0	3	0	1
T73	1736	0	0	0
T78	0	4	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	3001	0	88
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	4	0	0
T26	2735	16	0	1
T27	1501	0	0	0
T36	2168	0	0	0
T44	0	4	0	0
T46	2279	0	0	0
T55	0	3	0	1
T67	0	1	0	0
T70	0	3	0	1
T73	1736	0	0	0
T80	0	3	0	1
T81	0	4	0	0
T82	0	3	0	1
T83	0	14	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	3599	0	82
T5	12980	0	0	0
T6	2847	0	0	0
T10	0	37	0	1
T13	2695	3	0	1
T14	1696	0	0	0
T21	3193	0	0	0
T22	2304	0	0	0
T23	2573	0	0	0
T36	2168	1	0	0
T45	0	9	0	1
T46	2279	0	0	0
T48	0	3	0	1
T52	0	48	0	1
T53	0	4	0	1
T55	0	7	0	1
T70	0	3	0	1
T73	1736	0	0	0
T80	0	0	0	1
T88	0	8	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	573673	0	314
T1	2845	426	0	0
T2	2811	199	0	0
T3	2896	362	0	0
T4	636609	1573	0	2
T6	0	0	0	2
T13	2695	198	0	0
T17	1773	182	0	0
T18	0	0	0	2
T21	0	0	0	2
T23	2573	295	0	0
T24	0	0	0	2
T25	817	70	0	0
T26	2735	14	0	0
T27	1501	43	0	0
T41	0	0	0	2
T42	0	0	0	2
T67	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	2759	0	72
T5	12980	0	0	0
T6	2847	0	0	0
T10	0	3	0	1
T13	2695	52	0	1
T14	1696	0	0	0
T21	3193	0	0	0
T22	2304	0	0	0
T23	2573	0	0	0
T36	2168	0	0	0
T44	0	4	0	1
T45	0	3	0	1
T46	2279	0	0	0
T54	0	4	0	0
T55	0	48	0	1
T73	1736	0	0	0
T80	0	14	0	1
T84	0	0	0	1
T89	0	1	0	0
T90	0	4	0	0
T91	0	3	0	1
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	153754	0	0
T7	0	382	0	0
T8	0	1104	0	0
T14	1696	364	0	0
T15	0	669	0	0
T16	0	920	0	0
T18	0	19190	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1114	0	0
T37	643	205	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	625	0	0
T75	0	575	0	0