Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	224465447	10404918	0	0
boot_gen_cmd_rd_A	224465447	53186	0	0
boot_ins_cmd_rd_A	224465447	60210	0	0
ctrl_rd_A	224465447	52123	0	0
err_code_test_rd_A	224465447	60670	0	0
intr_enable_rd_A	224465447	58310	0	0
max_num_reqs_between_reseeds_rd_A	224465447	54039	0	0
regwen_rd_A	224465447	61255	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	10404918	0	0
T4	636609	215957	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T41	0	86869	0	0
T42	0	325160	0	0
T71	0	111734	0	0
T72	0	72709	0	0
T225	0	361725	0	0
T226	0	504290	0	0
T227	0	68219	0	0
T228	0	480292	0	0
T229	0	313309	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	53186	0	0
T4	636609	6562	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	9487	0	0
T230	0	2136	0	0
T231	0	2694	0	0
T232	0	3911	0	0
T233	0	5700	0	0
T234	0	7121	0	0
T235	0	5095	0	0
T236	0	2067	0	0
T237	0	4903	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	60210	0	0
T4	636609	7028	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	10018	0	0
T230	0	2272	0	0
T231	0	3047	0	0
T232	0	4954	0	0
T233	0	6146	0	0
T234	0	7975	0	0
T235	0	6267	0	0
T236	0	2230	0	0
T237	0	5881	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	52123	0	0
T4	636609	6079	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T29	0	3	0	0
T30	0	3	0	0
T36	2168	0	0	0
T202	0	8947	0	0
T230	0	1794	0	0
T231	0	2843	0	0
T232	0	3965	0	0
T238	0	9	0	0
T239	0	8	0	0
T240	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	60670	0	0
T4	636609	7058	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	10661	0	0
T230	0	2410	0	0
T231	0	2953	0	0
T232	0	4676	0	0
T233	0	6492	0	0
T234	0	8207	0	0
T235	0	5840	0	0
T236	0	2240	0	0
T237	0	5560	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	58310	0	0
T4	636609	6041	0	0
T5	12980	13	0	0
T6	2847	24	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	9732	0	0
T230	0	2421	0	0
T231	0	2973	0	0
T232	0	4318	0	0
T241	0	59	0	0
T242	0	50	0	0
T243	0	37	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	54039	0	0
T4	636609	6528	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	8830	0	0
T230	0	2106	0	0
T231	0	2777	0	0
T232	0	3886	0	0
T233	0	5694	0	0
T234	0	7479	0	0
T235	0	4875	0	0
T236	0	1987	0	0
T237	0	5198	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224465447	61255	0	0
T4	636609	6781	0	0
T5	12980	0	0	0
T6	2847	0	0	0
T13	2695	0	0	0
T21	3193	0	0	0
T23	2573	0	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T36	2168	0	0	0
T202	0	10449	0	0
T230	0	2629	0	0
T231	0	3193	0	0
T232	0	4845	0	0
T233	0	6057	0	0
T234	0	8417	0	0
T235	0	5857	0	0
T236	0	2160	0	0
T237	0	5743	0	0