Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.86 100.00 71.43 100.00 100.00 u_prim_fifo_sync_rescmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_secure_ptrs.u_rptr 100.00 100.00
gen_secure_ptrs.u_wptr 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.64 100.00 78.57 100.00 100.00 u_prim_fifo_sync_gencmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_secure_ptrs.u_rptr 100.00 100.00
gen_secure_ptrs.u_wptr 100.00 100.00

Line Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
109 1 1


Cond Coverage for Module : prim_fifo_sync_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT3,T9,T10
10CoveredT3,T9,T10
11CoveredT3,T9,T10

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT3,T9,T10
11CoveredT9,T11,T20

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T11
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T11
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T3,T9,T10
0 1 Covered T1,T2,T3
0 0 Covered T9,T10,T11

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
109 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT10,T27,T20
10CoveredT3,T9,T10
11CoveredT10,T20,T21

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T27,T20

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT10,T20,T22
10CoveredT9,T10,T11
11CoveredT20,T22,T23

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T20,T22

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T21,T91

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T21,T91

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT10,T20,T22
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT10,T20,T22
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T20,T21,T91
0 1 Covered T1,T2,T3
0 0 Covered T10,T20,T22

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
109 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT3,T9,T10
10CoveredT3,T9,T10
11CoveredT3,T9,T10

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T11,T24
10CoveredT3,T9,T10
11CoveredT9,T11,T24

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T11,T24

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T10

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T11,T69
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T11,T69
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T3,T9,T10
0 1 Covered T1,T2,T3
0 0 Covered T9,T11,T69

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%