Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T90
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T36,T37
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486994300	1150711	0	0
DepthKnown_A	487678298	487319898	0	0
RvalidKnown_A	487678298	487319898	0	0
WreadyKnown_A	487678298	487319898	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	487354624	1226300	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486994300	1150711	0	0
T3	5276	821	0	0
T4	12730	0	0	0
T9	5754	1643	0	0
T10	12386	9349	0	0
T11	4238	1773	0	0
T20	0	3380	0	0
T25	2068	0	0	0
T26	3482	0	0	0
T27	5050	473	0	0
T28	4540	0	0	0
T31	3840	0	0	0
T40	0	4941	0	0
T56	0	43	0	0
T78	0	658	0	0
T85	0	531	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487678298	487319898	0	0
T1	2278	1950	0	0
T2	3536	3394	0	0
T3	5276	5088	0	0
T4	12730	12482	0	0
T9	5754	5626	0	0
T10	12386	12214	0	0
T25	2068	1930	0	0
T26	3482	3330	0	0
T27	5050	4856	0	0
T28	4540	4402	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487678298	487319898	0	0
T1	2278	1950	0	0
T2	3536	3394	0	0
T3	5276	5088	0	0
T4	12730	12482	0	0
T9	5754	5626	0	0
T10	12386	12214	0	0
T25	2068	1930	0	0
T26	3482	3330	0	0
T27	5050	4856	0	0
T28	4540	4402	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487678298	487319898	0	0
T1	2278	1950	0	0
T2	3536	3394	0	0
T3	5276	5088	0	0
T4	12730	12482	0	0
T9	5754	5626	0	0
T10	12386	12214	0	0
T25	2068	1930	0	0
T26	3482	3330	0	0
T27	5050	4856	0	0
T28	4540	4402	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	487354624	1226300	0	0
T3	5276	821	0	0
T4	12730	0	0	0
T9	5754	1643	0	0
T10	12386	9349	0	0
T11	4238	1773	0	0
T15	0	294	0	0
T20	0	3380	0	0
T25	2068	0	0	0
T26	3482	0	0	0
T27	5050	473	0	0
T28	4540	0	0	0
T31	3840	0	0	0
T40	0	4941	0	0
T56	0	43	0	0
T85	0	531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T92,T93
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	243497150	569578	0	0
DepthKnown_A	243839149	243659949	0	0
RvalidKnown_A	243839149	243659949	0	0
WreadyKnown_A	243839149	243659949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	243677312	607046	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243497150	569578	0	0
T3	2638	406	0	0
T4	6365	0	0	0
T9	2877	771	0	0
T10	6193	4647	0	0
T11	2119	850	0	0
T20	0	1686	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	231	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T40	0	2426	0	0
T56	0	9	0	0
T78	0	308	0	0
T85	0	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	243677312	607046	0	0
T3	2638	406	0	0
T4	6365	0	0	0
T9	2877	771	0	0
T10	6193	4647	0	0
T11	2119	850	0	0
T15	0	148	0	0
T20	0	1686	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	231	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T40	0	2426	0	0
T56	0	9	0	0
T85	0	261	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T90
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T37,T94
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	243497150	581133	0	0
DepthKnown_A	243839149	243659949	0	0
RvalidKnown_A	243839149	243659949	0	0
WreadyKnown_A	243839149	243659949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	243677312	619254	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243497150	581133	0	0
T3	2638	415	0	0
T4	6365	0	0	0
T9	2877	872	0	0
T10	6193	4702	0	0
T11	2119	923	0	0
T20	0	1694	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	242	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T40	0	2515	0	0
T56	0	34	0	0
T78	0	350	0	0
T85	0	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	243677312	619254	0	0
T3	2638	415	0	0
T4	6365	0	0	0
T9	2877	872	0	0
T10	6193	4702	0	0
T11	2119	923	0	0
T15	0	146	0	0
T20	0	1694	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	242	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T40	0	2515	0	0
T56	0	34	0	0
T85	0	270	0	0