Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.26	98.25	93.73	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.17	99.92	92.41	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T27

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T14,T15

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T38,T39	Yes	T5,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T9,T10,T25	Yes	T9,T10,T25	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T9,T40	Yes	T2,T9,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T9,T27	Yes	T1,T9,T27	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T41,T42	Yes	T3,T41,T42	INPUT
edn_i[4].edn_req	Yes	Yes	T9,T41,T42	Yes	T9,T41,T42	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T40,T42	Yes	T9,T40,T42	INPUT
edn_i[6].edn_req	Yes	Yes	T28,T40,T41	Yes	T28,T40,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T9,T10,T25	Yes	T9,T10,T25	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T9,T10,T25	Yes	T9,T10,T25	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T9,T40	Yes	T2,T9,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T9,T40,T14	Yes	T2,T9,T40	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T9,T40	Yes	T2,T9,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T9,T27,T11	Yes	T9,T27,T11	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T11,T40,T43	Yes	T11,T44,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T9,T27	Yes	T1,T9,T27	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T41,T42	Yes	T3,T41,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T41,T45,T46	Yes	T3,T41,T42	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T41,T42	Yes	T3,T41,T42	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T9,T42,T45	Yes	T9,T41,T42	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T42,T45	Yes	T9,T42,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T9,T41,T42	Yes	T9,T41,T42	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T40,T42	Yes	T9,T40,T42	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T40,T45,T47	Yes	T40,T42,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T40,T42	Yes	T9,T40,T42	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T40,T41,T45	Yes	T40,T41,T45	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T45,T48	Yes	T40,T41,T45	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T28,T40,T41	Yes	T28,T40,T41	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T14,T49	Yes	T1,T14,T49	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T14,T49	Yes	T1,T14,T49	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T50	Yes	T4,T5,T50	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	243839149	243659949	0	0
CsrngAppIfOut_A	243839149	243659949	0	0
FpvSecCmCntAlertCheck_A	243839149	120	0	0
FpvSecCmGenCmdFifoRptrCheck_A	243839149	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	243839149	70	0	0
FpvSecCmMainFsmCheck_A	243839149	70	0	0
FpvSecCmRegWeOnehotCheck_A	243839149	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	243839149	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	243839149	70	0	0
IntrEdnCmdReqDoneKnownO_A	243839149	243659949	0	0
TlAReadyKnownO_A	243839149	243659949	0	0
TlDValidKnownO_A	243839149	243659949	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	243839149	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[0].EdnDataStable_A	243839149	31335	0	420
gen_edn_if_asserts[0].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[1].EdnDataStable_A	243839149	3311	0	124
gen_edn_if_asserts[1].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[2].EdnDataStable_A	243839149	5295	0	131
gen_edn_if_asserts[2].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[3].EdnDataStable_A	243839149	5768	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[4].EdnDataStable_A	243839149	56290	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[5].EdnDataStable_A	243839149	3594	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	243839149	149251	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	243839149	594108	0	322
gen_edn_if_asserts[6].EdnDataStable_A	243839149	2038	0	86
gen_edn_if_asserts[6].EdnEndPointOut_A	243839149	243659949	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	243839149	149251	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	120	0	0
T14	1042	1	0	0
T15	1737	1	0	0
T16	0	1	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T20	3151	0	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1642	0	0	0
T56	1565	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	70	0	0
T17	51881	20	0	0
T18	0	10	0	0
T19	0	20	0	0
T57	0	20	0	0
T58	912	0	0	0
T59	18609	0	0	0
T60	2929	0	0	0
T61	1798	0	0	0
T62	514	0	0	0
T63	1225	0	0	0
T64	1751	0	0	0
T65	1912	0	0	0
T66	8463	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	31335	0	420
T5	0	128	0	0
T9	2877	15	0	1
T10	6193	874	0	1
T11	2119	0	0	0
T25	1034	3	0	1
T26	1741	19	0	1
T27	2525	0	0	0
T28	2270	0	0	0
T31	1920	8	0	1
T42	0	3	0	1
T44	1885	0	0	0
T45	0	3	0	1
T46	0	0	0	1
T50	0	13	0	1
T73	1766	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	3311	0	124
T2	1768	4	0	1
T3	2638	0	0	0
T4	6365	0	0	0
T9	2877	7	0	1
T10	6193	0	0	0
T11	2119	0	0	0
T14	0	1	0	0
T24	0	0	0	1
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T40	0	317	0	1
T42	0	6	0	1
T45	0	41	0	1
T46	0	3	0	1
T48	0	61	0	1
T56	0	4	0	1
T78	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	5295	0	131
T1	1139	1	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T9	2877	3	0	1
T10	6193	0	0	0
T11	0	68	0	1
T20	0	4	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	4	0	1
T28	2270	0	0	0
T40	0	60	0	1
T42	0	13	0	1
T44	0	4	0	1
T45	0	8	0	1
T46	0	3	0	1
T48	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	5768	0	106
T3	2638	4	0	1
T4	6365	0	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T11	2119	0	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T41	0	44	0	1
T42	0	12	0	1
T45	0	27	0	1
T46	0	61	0	1
T48	0	41	0	1
T61	0	0	0	1
T80	0	4	0	1
T81	0	19	0	1
T82	0	9	0	1
T83	0	4	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	56290	0	100
T9	2877	48	0	1
T10	6193	0	0	0
T11	2119	0	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T41	0	3	0	1
T42	0	4	0	1
T44	1885	0	0	0
T45	0	60	0	1
T46	0	57	0	1
T48	0	3	0	1
T55	0	29	0	1
T73	1766	0	0	0
T81	0	3	0	1
T82	0	16	0	1
T84	0	40	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	3594	0	96
T9	2877	3	0	1
T10	6193	0	0	0
T11	2119	0	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T31	1920	0	0	0
T40	0	40	0	1
T42	0	3	0	1
T44	1885	0	0	0
T45	0	49	0	1
T46	0	3	0	1
T48	0	3	0	1
T73	1766	0	0	0
T81	0	3	0	1
T85	0	4	0	1
T86	0	4	0	0
T87	0	3	0	1
T88	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	594108	0	322
T1	1139	516	0	0
T2	1768	180	0	0
T3	2638	195	0	0
T4	6365	3038	0	2
T5	0	0	0	2
T9	2877	476	0	0
T10	6193	203	0	0
T20	0	0	0	2
T25	1034	11	0	0
T26	1741	39	0	0
T27	2525	374	0	0
T28	2270	304	0	0
T49	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	2038	0	86
T5	543505	0	0	0
T11	2119	0	0	0
T14	1042	0	0	0
T21	0	4	0	1
T28	2270	4	0	1
T31	1920	0	0	0
T40	5481	10	0	1
T41	2786	27	0	1
T44	1885	0	0	0
T45	0	19	0	1
T46	0	3	0	1
T48	0	27	0	1
T49	1415	0	0	0
T73	1766	0	0	0
T81	0	3	0	1
T86	0	4	0	1
T89	0	4	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	149251	0	0
T1	1139	7	0	0
T2	1768	0	0	0
T3	2638	0	0	0
T4	6365	0	0	0
T6	0	1124	0	0
T9	2877	0	0	0
T10	6193	0	0	0
T14	0	480	0	0
T15	0	1034	0	0
T16	0	634	0	0
T25	1034	0	0	0
T26	1741	0	0	0
T27	2525	0	0	0
T28	2270	0	0	0
T33	0	355	0	0
T74	0	1136	0	0
T75	0	267	0	0
T76	0	1068	0	0
T77	0	350	0	0