Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	244358329	10558427	0	0
boot_gen_cmd_rd_A	244358329	69805	0	0
boot_ins_cmd_rd_A	244358329	79393	0	0
ctrl_rd_A	244358329	70845	0	0
err_code_test_rd_A	244358329	81065	0	0
intr_enable_rd_A	244358329	78448	0	0
max_num_reqs_between_reseeds_rd_A	244358329	71564	0	0
regwen_rd_A	244358329	81412	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	10558427	0	0
T5	543505	218340	0	0
T14	1042	0	0	0
T15	1737	0	0	0
T20	3151	0	0	0
T38	0	137321	0	0
T39	0	164912	0	0
T40	5481	0	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T100	0	488620	0	0
T228	0	51323	0	0
T229	0	54238	0	0
T230	0	39818	0	0
T231	0	75254	0	0
T232	0	233447	0	0
T233	0	229937	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	69805	0	0
T7	662	0	0	0
T100	130716	7475	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	729	0	0
T229	0	1835	0	0
T234	0	4742	0	0
T235	0	7008	0	0
T236	0	3459	0	0
T237	0	7139	0	0
T238	0	5522	0	0
T239	0	6589	0	0
T240	0	8520	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	79393	0	0
T7	662	0	0	0
T100	130716	8706	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	972	0	0
T229	0	1729	0	0
T234	0	5634	0	0
T235	0	8212	0	0
T236	0	4016	0	0
T237	0	8162	0	0
T238	0	6239	0	0
T239	0	7717	0	0
T240	0	9102	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	70845	0	0
T6	0	5	0	0
T16	0	2	0	0
T22	4195	0	0	0
T24	2966	0	0	0
T29	0	9	0	0
T70	834	0	0	0
T74	2947	0	0	0
T89	2327	0	0	0
T95	10266	0	0	0
T99	2238	0	0	0
T100	0	7115	0	0
T101	2886	0	0	0
T143	0	1	0	0
T228	0	821	0	0
T229	0	1539	0	0
T245	3502	6	0	0
T246	0	7	0	0
T247	0	3	0	0
T248	1683	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	81065	0	0
T7	662	0	0	0
T100	130716	8796	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	777	0	0
T229	0	1748	0	0
T234	0	5503	0	0
T235	0	8566	0	0
T236	0	4025	0	0
T237	0	8203	0	0
T238	0	6750	0	0
T239	0	7681	0	0
T240	0	9662	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	78448	0	0
T7	662	0	0	0
T100	130716	7957	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	1117	0	0
T229	0	2218	0	0
T234	0	5342	0	0
T235	0	7699	0	0
T236	0	3765	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0
T249	0	98	0	0
T250	0	15	0	0
T251	0	58	0	0
T252	0	35	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	71564	0	0
T7	662	0	0	0
T100	130716	7540	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	713	0	0
T229	0	1584	0	0
T234	0	4974	0	0
T235	0	7470	0	0
T236	0	3586	0	0
T237	0	6863	0	0
T238	0	5505	0	0
T239	0	6766	0	0
T240	0	8295	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244358329	81412	0	0
T7	662	0	0	0
T100	130716	9018	0	0
T106	1683	0	0	0
T143	2706	0	0	0
T152	2461	0	0	0
T188	2634	0	0	0
T228	0	943	0	0
T229	0	1752	0	0
T234	0	5120	0	0
T235	0	8178	0	0
T236	0	3525	0	0
T237	0	8435	0	0
T238	0	6358	0	0
T239	0	8046	0	0
T240	0	9505	0	0
T241	3788	0	0	0
T242	2113	0	0	0
T243	13874	0	0	0
T244	2412	0	0	0