Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	206881994	9259114	0	0
boot_gen_cmd_rd_A	206881994	57711	0	0
boot_ins_cmd_rd_A	206881994	65651	0	0
ctrl_rd_A	206881994	58101	0	0
err_code_test_rd_A	206881994	65161	0	0
intr_enable_rd_A	206881994	63992	0	0
max_num_reqs_between_reseeds_rd_A	206881994	58305	0	0
regwen_rd_A	206881994	65457	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	9259114	0	0
T39	575476	34080	0	0
T40	0	183665	0	0
T41	0	121003	0	0
T69	705	0	0	0
T70	1184	0	0	0
T71	1549	0	0	0
T72	1792	0	0	0
T78	2098	0	0	0
T86	1169	0	0	0
T104	0	301619	0	0
T202	1006	0	0	0
T209	0	194932	0	0
T235	0	187416	0	0
T236	0	50998	0	0
T237	0	118238	0	0
T238	0	250765	0	0
T239	0	513634	0	0
T240	2096	0	0	0
T241	1986	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	57711	0	0
T40	531991	5591	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	3172	0	0
T235	0	5197	0	0
T236	0	743	0	0
T237	0	3585	0	0
T242	0	6364	0	0
T243	0	2566	0	0
T244	0	2668	0	0
T245	0	2763	0	0
T246	0	1478	0	0
T247	1803	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	65651	0	0
T40	531991	6575	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	3393	0	0
T235	0	6141	0	0
T236	0	888	0	0
T237	0	4073	0	0
T242	0	7573	0	0
T243	0	2929	0	0
T244	0	3363	0	0
T245	0	2887	0	0
T246	0	1788	0	0
T247	1803	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	58101	0	0
T40	531991	5385	0	0
T41	210023	0	0	0
T50	0	3	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	3293	0	0
T235	0	5235	0	0
T236	0	807	0	0
T237	0	3421	0	0
T242	0	6600	0	0
T247	1803	0	0	0
T248	0	1	0	0
T249	0	6	0	0
T250	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	65161	0	0
T40	531991	6433	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	3633	0	0
T235	0	6024	0	0
T236	0	978	0	0
T237	0	3898	0	0
T242	0	7061	0	0
T243	0	2708	0	0
T244	0	3258	0	0
T245	0	3176	0	0
T246	0	1732	0	0
T247	1803	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	63992	0	0
T40	531991	5700	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T105	0	36	0	0
T107	0	18	0	0
T197	2400	0	0	0
T209	0	3402	0	0
T235	0	5938	0	0
T236	0	942	0	0
T237	0	3736	0	0
T242	0	6757	0	0
T247	1803	0	0	0
T251	0	10	0	0
T252	0	111	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	58305	0	0
T40	531991	5366	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	2930	0	0
T235	0	5429	0	0
T236	0	727	0	0
T237	0	3630	0	0
T242	0	6487	0	0
T243	0	2438	0	0
T244	0	2695	0	0
T245	0	2429	0	0
T246	0	1589	0	0
T247	1803	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206881994	65457	0	0
T40	531991	6006	0	0
T41	210023	0	0	0
T52	13773	0	0	0
T68	35164	0	0	0
T73	3567	0	0	0
T74	2852	0	0	0
T79	1943	0	0	0
T104	740564	0	0	0
T197	2400	0	0	0
T209	0	3309	0	0
T235	0	5833	0	0
T236	0	847	0	0
T237	0	3835	0	0
T242	0	7219	0	0
T243	0	2573	0	0
T244	0	3121	0	0
T245	0	2973	0	0
T246	0	1942	0	0
T247	1803	0	0	0