Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.50	98.25	93.91	97.07	93.60	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.45	99.92	92.66	82.84	93.60	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T31,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T17,T18
1	0	Covered	T4,T5,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T5,T31	Yes	T3,T5,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T23	Yes	T2,T3,T24	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T23,T26	Yes	T3,T23,T26	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T26,T10	Yes	T2,T26,T10	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T25,T26	Yes	T2,T25,T26	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	INPUT
edn_i[4].edn_req	Yes	Yes	T26,T42,T43	Yes	T26,T42,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T5,T26	Yes	T2,T5,T26	INPUT
edn_i[6].edn_req	Yes	Yes	T44,T12,T45	Yes	T44,T12,T45	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T23,T26,T27	Yes	T3,T23,T26	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T27,T46,T10	Yes	T27,T46,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T23,T26	Yes	T3,T23,T26	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T26,T10	Yes	T2,T26,T10	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T10,T47	Yes	T26,T10,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T26,T10	Yes	T2,T26,T10	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T25,T26	Yes	T2,T25,T26	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T2,T25,T46	Yes	T2,T25,T16	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T25,T26	Yes	T2,T25,T26	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T26,T48	Yes	T2,T24,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T4,T26,T48	Yes	T2,T4,T26	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T26,T42,T43	Yes	T26,T42,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T26,T42,T49	Yes	T26,T42,T49	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T26,T42,T43	Yes	T26,T42,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T26,T48	Yes	T2,T26,T48	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T26,T48	Yes	T2,T26,T48	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T26,T48	Yes	T2,T26,T48	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T44,T12,T45	Yes	T44,T12,T45	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T12,T45,T50	Yes	T44,T12,T45	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T44,T12,T45	Yes	T44,T12,T45	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T25	Yes	T1,T2,T26	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T26,T27	Yes	T1,T2,T26	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T16,T31,T32	Yes	T16,T31,T32	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T51,T31	Yes	T16,T51,T31	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T51	Yes	T4,T5,T51	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T51,T31	Yes	T16,T51,T31	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T51	Yes	T4,T5,T51	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T39,T40,T52	Yes	T39,T40,T52	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T53,T39	Yes	T4,T53,T39	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	206319264	206136775	0	0
CsrngAppIfOut_A	206319264	206136775	0	0
FpvSecCmCntAlertCheck_A	206319264	110	0	0
FpvSecCmGenCmdFifoRptrCheck_A	206319264	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	206319264	70	0	0
FpvSecCmMainFsmCheck_A	206319264	70	0	0
FpvSecCmRegWeOnehotCheck_A	206319264	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	206319264	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	206319264	70	0	0
IntrEdnCmdReqDoneKnownO_A	206319264	206136775	0	0
TlAReadyKnownO_A	206319264	206136775	0	0
TlDValidKnownO_A	206319264	206136775	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	206319264	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[0].EdnDataStable_A	206319264	78213	0	417
gen_edn_if_asserts[0].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[1].EdnDataStable_A	206319264	5776	0	129
gen_edn_if_asserts[1].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[2].EdnDataStable_A	206319264	2983	0	113
gen_edn_if_asserts[2].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[3].EdnDataStable_A	206319264	4719	0	109
gen_edn_if_asserts[3].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[4].EdnDataStable_A	206319264	5057	0	84
gen_edn_if_asserts[4].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[5].EdnDataStable_A	206319264	3226	0	80
gen_edn_if_asserts[5].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	206319264	143484	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	206319264	585628	0	330
gen_edn_if_asserts[6].EdnDataStable_A	206319264	2596	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	206319264	206136775	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	206319264	143484	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	110	0	0
T5	2987	1	0	0
T6	0	1	0	0
T10	3142	0	0	0
T15	0	20	0	0
T16	2148	0	0	0
T17	0	20	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T31	2199	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	70	0	0
T15	47380	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	0	0	0
T54	803	0	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	78213	0	417
T3	1430	3	0	1
T4	2007	0	0	0
T5	2987	0	0	0
T10	0	20	0	1
T14	0	22	0	1
T16	2148	0	0	0
T23	825	4	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	7	0	1
T27	3789	9	0	1
T31	0	8	0	1
T32	0	4	0	1
T42	0	0	0	1
T46	1546	19	0	1
T48	0	10	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	5776	0	129
T2	3069	3	0	1
T3	1430	0	0	0
T4	2007	0	0	0
T5	2987	0	0	0
T10	0	55	0	1
T16	2148	0	0	0
T19	0	57	0	1
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	58	0	1
T27	3789	0	0	0
T45	0	13	0	1
T47	0	11	0	1
T49	0	55	0	1
T71	0	8	0	1
T72	0	4	0	0
T73	0	20	0	1
T74	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	2983	0	113
T2	3069	45	0	1
T3	1430	0	0	0
T4	2007	0	0	0
T5	2987	0	0	0
T10	0	3	0	1
T11	0	4	0	1
T16	2148	4	0	1
T19	0	3	0	1
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	3	0	1
T26	2260	3	0	1
T27	3789	0	0	0
T42	0	7	0	1
T46	0	59	0	1
T47	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	4719	0	109
T1	1718	4	0	0
T2	3069	3	0	1
T3	1430	0	0	0
T4	2007	1	0	0
T5	2987	0	0	0
T23	825	0	0	0
T24	2255	3	0	1
T25	1072	0	0	0
T26	2260	23	0	1
T27	3789	0	0	0
T45	0	0	0	1
T47	0	3	0	1
T48	0	18	0	1
T53	0	1	0	0
T75	0	22	0	1
T76	0	4	0	1
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	5057	0	84
T10	3142	0	0	0
T16	2148	0	0	0
T26	2260	49	0	1
T27	3789	0	0	0
T31	2199	0	0	0
T32	2002	0	0	0
T42	0	25	0	1
T43	0	4	0	1
T45	0	42	0	1
T46	1546	0	0	0
T47	1473	0	0	0
T48	3349	0	0	0
T49	0	62	0	1
T51	1464	0	0	0
T79	0	4	0	1
T80	0	1	0	0
T81	0	4	0	0
T82	0	3	0	1
T83	0	52	0	1
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	3226	0	80
T2	3069	43	0	1
T3	1430	0	0	0
T4	2007	0	0	0
T5	2987	0	0	0
T16	2148	0	0	0
T21	0	4	0	0
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	20	0	1
T27	3789	0	0	0
T45	0	3	0	1
T48	0	77	0	1
T49	0	51	0	1
T78	0	4	0	0
T79	0	4	0	0
T82	0	0	0	1
T83	0	0	0	1
T86	0	4	0	0
T87	0	54	0	1
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	585628	0	330
T1	1718	739	0	2
T2	3069	22	0	0
T3	1430	17	0	0
T4	2007	1024	0	0
T5	2987	1146	0	0
T15	0	0	0	2
T23	825	31	0	0
T24	2255	55	0	0
T25	1072	100	0	0
T26	2260	30	0	0
T27	3789	12	0	0
T39	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T64	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	2596	0	75
T12	0	28	0	1
T19	1790	0	0	0
T22	3164	0	0	0
T43	1818	0	0	0
T44	643	3	0	1
T45	0	63	0	1
T50	0	4	0	0
T54	803	0	0	0
T62	861	0	0	0
T63	1683	0	0	0
T64	1312	0	0	0
T65	1504	0	0	0
T83	0	5	0	1
T85	0	3	0	1
T87	0	15	0	1
T90	0	3	0	1
T91	0	1	0	0
T92	0	74	0	1
T93	2592	0	0	0
T94	0	0	0	1
T95	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	143484	0	0
T4	2007	1070	0	0
T5	2987	1165	0	0
T6	0	657	0	0
T10	3142	0	0	0
T15	0	14298	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	230	0	0
T54	0	404	0	0
T55	0	1137	0	0
T63	0	309	0	0
T69	0	277	0	0
T70	0	600	0	0