Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.95 95.02 97.57 100.00 92.16 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_alert 100.00 100.00
u_alert_test_recov_alert 100.00 100.00
u_boot_gen_cmd 100.00 100.00 100.00 100.00
u_boot_ins_cmd 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_ctrl_auto_req_mode 100.00 100.00 100.00 100.00
u_ctrl_boot_req_mode 100.00 100.00 100.00 100.00
u_ctrl_cmd_fifo_rst 100.00 100.00 100.00 100.00
u_ctrl_edn_enable 100.00 100.00 100.00 100.00
u_err_code_edn_ack_sm_err 96.30 88.89 100.00 100.00
u_err_code_edn_cntr_err 96.30 88.89 100.00 100.00
u_err_code_edn_main_sm_err 96.30 88.89 100.00 100.00
u_err_code_fifo_read_err 96.30 88.89 100.00 100.00
u_err_code_fifo_state_err 96.30 88.89 100.00 100.00
u_err_code_fifo_write_err 96.30 88.89 100.00 100.00
u_err_code_sfifo_gencmd_err 96.30 88.89 100.00 100.00
u_err_code_sfifo_rescmd_err 96.30 88.89 100.00 100.00
u_err_code_test 100.00 100.00 100.00 100.00
u_err_code_test0_qe 100.00 100.00 100.00
u_generate_cmd 100.00 100.00
u_hw_cmd_sts_auto_mode 62.59 77.78 50.00 60.00
u_hw_cmd_sts_boot_mode 62.59 77.78 50.00 60.00
u_hw_cmd_sts_cmd_ack 62.59 77.78 50.00 60.00
u_hw_cmd_sts_cmd_sts 62.59 77.78 50.00 60.00
u_hw_cmd_sts_cmd_type 62.59 77.78 50.00 60.00
u_intr_enable_edn_cmd_req_done 100.00 100.00 100.00 100.00
u_intr_enable_edn_fatal_err 100.00 100.00 100.00 100.00
u_intr_state_edn_cmd_req_done 100.00 100.00 100.00 100.00
u_intr_state_edn_fatal_err 100.00 100.00 100.00 100.00
u_intr_test_edn_cmd_req_done 100.00 100.00
u_intr_test_edn_fatal_err 100.00 100.00
u_main_sm_state 62.59 77.78 50.00 60.00
u_max_num_reqs_between_reseeds 100.00 100.00 100.00 100.00
u_max_num_reqs_between_reseeds0_qe 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_recov_alert_sts_auto_req_mode_field_alert 100.00 100.00 100.00 100.00
u_recov_alert_sts_boot_req_mode_field_alert 100.00 100.00 100.00 100.00
u_recov_alert_sts_cmd_fifo_rst_field_alert 100.00 100.00 100.00 100.00
u_recov_alert_sts_csrng_ack_err 100.00 100.00 100.00 100.00
u_recov_alert_sts_edn_bus_cmp_alert 100.00 100.00 100.00 100.00
u_recov_alert_sts_edn_enable_field_alert 100.00 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_regwen 100.00 100.00 100.00 100.00
u_reseed_cmd 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_sw_cmd_req 100.00 100.00
u_sw_cmd_sts_cmd_ack 62.59 77.78 50.00 60.00
u_sw_cmd_sts_cmd_rdy 62.59 77.78 50.00 60.00
u_sw_cmd_sts_cmd_reg_rdy 62.59 77.78 50.00 60.00
u_sw_cmd_sts_cmd_sts 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : edn_reg_top
Line No.TotalCoveredPercent
TOTAL152152100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN37011100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN58911100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN135211100.00
ALWAYS13861919100.00
CONT_ASSIGN140711100.00
ALWAYS141111100.00
CONT_ASSIGN143311100.00
CONT_ASSIGN143511100.00
CONT_ASSIGN143711100.00
CONT_ASSIGN143811100.00
CONT_ASSIGN144011100.00
CONT_ASSIGN144211100.00
CONT_ASSIGN144311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN144711100.00
CONT_ASSIGN144811100.00
CONT_ASSIGN145011100.00
CONT_ASSIGN145211100.00
CONT_ASSIGN145311100.00
CONT_ASSIGN145511100.00
CONT_ASSIGN145611100.00
CONT_ASSIGN145811100.00
CONT_ASSIGN146011100.00
CONT_ASSIGN146211100.00
CONT_ASSIGN146411100.00
CONT_ASSIGN146511100.00
CONT_ASSIGN146711100.00
CONT_ASSIGN146811100.00
CONT_ASSIGN147011100.00
CONT_ASSIGN147111100.00
CONT_ASSIGN147311100.00
CONT_ASSIGN147411100.00
CONT_ASSIGN147611100.00
CONT_ASSIGN147711100.00
CONT_ASSIGN147911100.00
CONT_ASSIGN148011100.00
CONT_ASSIGN148211100.00
CONT_ASSIGN148311100.00
CONT_ASSIGN148511100.00
CONT_ASSIGN148711100.00
CONT_ASSIGN148911100.00
CONT_ASSIGN149111100.00
CONT_ASSIGN149311100.00
CONT_ASSIGN149511100.00
CONT_ASSIGN149611100.00
CONT_ASSIGN149811100.00
ALWAYS15021919100.00
ALWAYS15254646100.00
CONT_ASSIGN163600
CONT_ASSIGN164411100.00
CONT_ASSIGN164511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
318 1 1
333 1 1
349 1 1
355 1 1
370 1 1
386 1 1
420 1 1
589 1 1
603 1 1
856 1 1
870 1 1
876 1 1
890 1 1
930 1 1
1352 1 1
1386 1 1
1387 1 1
1388 1 1
1389 1 1
1390 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1400 1 1
1401 1 1
1402 1 1
1403 1 1
1404 1 1
1407 1 1
1411 1 1
1433 1 1
1435 1 1
1437 1 1
1438 1 1
1440 1 1
1442 1 1
1443 1 1
1445 1 1
1447 1 1
1448 1 1
1450 1 1
1452 1 1
1453 1 1
1455 1 1
1456 1 1
1458 1 1
1460 1 1
1462 1 1
1464 1 1
1465 1 1
1467 1 1
1468 1 1
1470 1 1
1471 1 1
1473 1 1
1474 1 1
1476 1 1
1477 1 1
1479 1 1
1480 1 1
1482 1 1
1483 1 1
1485 1 1
1487 1 1
1489 1 1
1491 1 1
1493 1 1
1495 1 1
1496 1 1
1498 1 1
1502 1 1
1503 1 1
1504 1 1
1505 1 1
1506 1 1
1507 1 1
1508 1 1
1509 1 1
1510 1 1
1511 1 1
1512 1 1
1513 1 1
1514 1 1
1515 1 1
1516 1 1
1517 1 1
1518 1 1
1519 1 1
1520 1 1
1525 1 1
1526 1 1
1528 1 1
1529 1 1
1533 1 1
1534 1 1
1538 1 1
1539 1 1
1543 1 1
1544 1 1
1548 1 1
1552 1 1
1553 1 1
1554 1 1
1555 1 1
1559 1 1
1563 1 1
1567 1 1
1571 1 1
1572 1 1
1573 1 1
1574 1 1
1578 1 1
1579 1 1
1580 1 1
1581 1 1
1582 1 1
1586 1 1
1590 1 1
1594 1 1
1598 1 1
1599 1 1
1600 1 1
1601 1 1
1602 1 1
1603 1 1
1607 1 1
1608 1 1
1609 1 1
1610 1 1
1611 1 1
1612 1 1
1613 1 1
1614 1 1
1618 1 1
1622 1 1
1636 unreachable
1644 1 1
1645 1 1


Cond Coverage for Module : edn_reg_top
TotalCoveredPercent
Conditions190190100.00
Logical190190100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T40,T41
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T17,T18
10CoveredT295,T296,T297

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T17,T18
010CoveredT295,T296,T297
100CoveredT15,T17,T18

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT295,T296,T297
010CoveredT39,T40,T41
100CoveredT39,T40,T41

 LINE       420
 EXPRESSION (ctrl_we & regwen_qs)
             ---1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       1387
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_STATE_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1388
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_ENABLE_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       1389
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_TEST_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T31

 LINE       1390
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ALERT_TEST_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T51,T31

 LINE       1391
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_REGWEN_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T31,T14

 LINE       1392
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_CTRL_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1393
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_INS_CMD_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T5,T25

 LINE       1394
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_GEN_CMD_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T23,T5

 LINE       1395
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_REQ_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1396
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_STS_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1397
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_HW_CMD_STS_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T16,T31

 LINE       1398
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RESEED_CMD_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T16

 LINE       1399
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_GENERATE_CMD_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1400
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T10

 LINE       1401
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RECOV_ALERT_STS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T31

 LINE       1402
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T31,T6

 LINE       1403
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_TEST_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T23,T24

 LINE       1404
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAIN_SM_STATE_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T31,T32

 LINE       1407
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1407
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       1411
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT1,T2,T3
11CoveredT39,T40,T41

 LINE       1411
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18-StatusTests
000000000000000000CoveredT1,T2,T3
000000000000000001CoveredT16,T31,T32
000000000000000010CoveredT5,T31,T14
000000000000000100CoveredT5,T31,T6
000000000000001000CoveredT5,T16,T31
000000000000010000CoveredT3,T31,T14
000000000000100000CoveredT3,T5,T31
000000000001000000CoveredT14,T108,T97
000000000010000000CoveredT31,T11,T14
000000000100000000CoveredT2,T3,T24
000000001000000000CoveredT31,T14,T108
000000010000000000CoveredT3,T5,T14
000000100000000000CoveredT5,T14,T108
000001000000000000CoveredT3,T5,T31
000010000000000000CoveredT3,T31,T14
000100000000000000CoveredT5,T31,T14
001000000000000000CoveredT14,T108,T97
010000000000000000CoveredT31,T14,T108
100000000000000000CoveredT2,T3,T23

 LINE       1411
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T24
10CoveredT1,T2,T3
11CoveredT2,T3,T23

 LINE       1411
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT3,T4,T5
11CoveredT31,T14,T108

 LINE       1411
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT3,T5,T31
11CoveredT14,T108,T97

 LINE       1411
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT5,T51,T31
11CoveredT5,T31,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT14,T108,T97
11CoveredT3,T31,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T5,T31

 LINE       1411
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T5,T25
11CoveredT5,T14,T108

 LINE       1411
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T5,T25
11CoveredT3,T5,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT31,T14,T108

 LINE       1411
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT1,T2,T3
11CoveredT2,T3,T24

 LINE       1411
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T16,T31
11CoveredT31,T11,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T16
11CoveredT14,T108,T97

 LINE       1411
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T16
11CoveredT3,T5,T31

 LINE       1411
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T11
11CoveredT3,T31,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T31,T32
11CoveredT5,T16,T31

 LINE       1411
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T15,T39
11CoveredT5,T31,T6

 LINE       1411
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T23
10CoveredT1,T23,T24
11CoveredT5,T31,T14

 LINE       1411
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T31,T32
11CoveredT16,T31,T32

 LINE       1433
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT39,T40,T41
111CoveredT1,T2,T3

 LINE       1438
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT39,T40,T41
111CoveredT4,T5,T6

 LINE       1443
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T5,T31
110CoveredT39,T40,T41
111CoveredT39,T40,T52

 LINE       1448
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT5,T51,T31
110CoveredT39,T40,T41
111CoveredT51,T64,T66

 LINE       1453
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T31,T14
110CoveredT39,T40,T41
111CoveredT28,T29,T30

 LINE       1456
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT39,T40,T41
111CoveredT1,T2,T3

 LINE       1465
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT23,T5,T25
110CoveredT39,T40,T41
111CoveredT23,T5,T25

 LINE       1468
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T23,T5
110CoveredT39,T40,T41
111CoveredT23,T5,T25

 LINE       1471
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT39,T40,T41
111CoveredT1,T2,T3

 LINE       1474
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T16
110CoveredT39,T40,T41
111CoveredT1,T5,T16

 LINE       1477
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT39,T40,T41
111CoveredT1,T5,T16

 LINE       1480
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T10
110CoveredT39,T40,T41
111CoveredT1,T10,T11

 LINE       1483
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT5,T16,T31
110CoveredT39,T40,T41
111CoveredT16,T31,T32

 LINE       1496
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T23,T24
110CoveredT39,T40,T41
111CoveredT1,T23,T24

Branch Coverage for Module : edn_reg_top
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 1407 2 2 100.00
IF 68 3 3 100.00
CASE 1526 19 19 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1407 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T17,T18
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1526 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T23
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T23
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T23
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T23
addr_hit[15] Covered T1,T2,T23
addr_hit[16] Covered T1,T2,T23
addr_hit[17] Covered T1,T2,T23
default Covered T1,T2,T3


Assert Coverage for Module : edn_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 206881994 734158 0 0
reAfterRv 206881994 734158 0 0
rePulse 206881994 278281 0 0
wePulse 206881994 455877 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 206881994 734158 0 0
T1 1718 68 0 0
T2 3069 324 0 0
T3 1430 28 0 0
T4 2007 36 0 0
T5 2987 20 0 0
T23 825 6 0 0
T24 2255 101 0 0
T25 1072 5 0 0
T26 2260 168 0 0
T27 3789 147 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 206881994 734158 0 0
T1 1718 68 0 0
T2 3069 324 0 0
T3 1430 28 0 0
T4 2007 36 0 0
T5 2987 20 0 0
T23 825 6 0 0
T24 2255 101 0 0
T25 1072 5 0 0
T26 2260 168 0 0
T27 3789 147 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 206881994 278281 0 0
T1 1718 12 0 0
T2 3069 289 0 0
T3 1430 21 0 0
T4 2007 26 0 0
T5 2987 5 0 0
T23 825 1 0 0
T24 2255 70 0 0
T25 1072 1 0 0
T26 2260 141 0 0
T27 3789 109 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 206881994 455877 0 0
T1 1718 56 0 0
T2 3069 35 0 0
T3 1430 7 0 0
T4 2007 10 0 0
T5 2987 15 0 0
T23 825 5 0 0
T24 2255 31 0 0
T25 1072 4 0 0
T26 2260 27 0 0
T27 3789 38 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%