Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T11,T12

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T4,T16,T17

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T22	Yes	T3,T10,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T10	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T35,T36	Yes	T6,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T37	Yes	T1,T2,T37	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T2,T38	Yes	T1,T2,T38	INPUT
edn_i[4].edn_req	Yes	Yes	T11,T37,T13	Yes	T11,T37,T13	INPUT
edn_i[5].edn_req	Yes	Yes	T13,T39,T40	Yes	T13,T39,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T37,T41,T14	Yes	T37,T41,T14	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T39,T40	Yes	T2,T3,T39	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T2,T37	Yes	T1,T2,T37	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T2,T38,T42	Yes	T1,T2,T13	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T37	Yes	T1,T2,T37	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T2,T38	Yes	T1,T2,T38	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T2,T43	Yes	T1,T2,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T2,T38	Yes	T1,T2,T38	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T11,T37,T13	Yes	T11,T37,T13	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T37,T13,T14	Yes	T11,T37,T13	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T11,T37,T13	Yes	T11,T37,T13	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T13,T39,T40	Yes	T13,T39,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T13,T44,T38	Yes	T13,T40,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T13,T39,T40	Yes	T13,T39,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T37,T41,T14	Yes	T37,T41,T14	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T14,T38,T45	Yes	T37,T41,T14	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T37,T41,T14	Yes	T37,T41,T14	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T10	Yes	T1,T2,T5	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T3,T12,T46	Yes	T3,T12,T46	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T11,T12	Yes	T3,T11,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T22,T47	Yes	T4,T22,T47	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T11,T12	Yes	T3,T11,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T22,T47	Yes	T4,T22,T47	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T23,T6	Yes	T5,T23,T6	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T23,T6,T35	Yes	T23,T6,T35	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	206999575	206829058	0	0
CsrngAppIfOut_A	206999575	206829058	0	0
FpvSecCmCntAlertCheck_A	206999575	107	0	0
FpvSecCmGenCmdFifoRptrCheck_A	206999575	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	206999575	60	0	0
FpvSecCmMainFsmCheck_A	206999575	60	0	0
FpvSecCmRegWeOnehotCheck_A	206999575	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	206999575	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	206999575	60	0	0
IntrEdnCmdReqDoneKnownO_A	206999575	206829058	0	0
TlAReadyKnownO_A	206999575	206829058	0	0
TlDValidKnownO_A	206999575	206829058	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	206999575	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[0].EdnDataStable_A	206999575	29684	0	422
gen_edn_if_asserts[0].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[1].EdnDataStable_A	206999575	6982	0	157
gen_edn_if_asserts[1].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[2].EdnDataStable_A	206999575	3807	0	137
gen_edn_if_asserts[2].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[3].EdnDataStable_A	206999575	3051	0	120
gen_edn_if_asserts[3].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[4].EdnDataStable_A	206999575	5052	0	109
gen_edn_if_asserts[4].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[5].EdnDataStable_A	206999575	1572	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	206999575	137972	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	206999575	574618	0	306
gen_edn_if_asserts[6].EdnDataStable_A	206999575	2608	0	88
gen_edn_if_asserts[6].EdnEndPointOut_A	206999575	206829058	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	206999575	137972	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	107	0	0
T4	451	1	0	0
T5	12250	0	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	20	0	0
T17	0	1	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1560	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	60	0	0
T7	569	0	0	0
T16	51233	20	0	0
T17	1782	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T45	2795	0	0	0
T56	0	10	0	0
T57	0	10	0	0
T58	1217	0	0	0
T59	1669	0	0	0
T60	2027	0	0	0
T61	2280	0	0	0
T62	2060	0	0	0
T63	2876	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	29684	0	422
T1	2516	54	0	1
T2	4298	42	0	1
T3	2087	0	0	0
T4	451	0	0	0
T5	12250	13	0	0
T6	0	26	0	0
T10	3140	15	0	1
T11	2336	0	0	0
T12	2053	0	0	0
T21	1153	15	0	1
T22	1203	0	0	0
T37	0	33	0	1
T39	0	3	0	1
T40	0	0	0	1
T55	0	7	0	1
T68	0	4	0	1
T69	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	6982	0	157
T2	4298	55	0	1
T3	2087	4	0	1
T4	451	0	0	0
T5	12250	0	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	4	0	1
T14	0	3	0	1
T20	0	4	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	0	3	0	1
T38	0	3	0	1
T39	0	34	0	1
T40	0	35	0	1
T46	0	4	0	1
T47	1313	0	0	0
T74	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	3807	0	137
T1	2516	3	0	1
T2	4298	18	0	1
T3	2087	0	0	0
T4	451	0	0	0
T5	12250	0	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T13	0	3	0	1
T14	0	3	0	1
T21	1153	0	0	0
T22	1203	0	0	0
T37	0	3	0	1
T38	0	19	0	1
T43	0	3	0	1
T75	0	4	0	1
T76	0	3	0	1
T77	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	3051	0	120
T1	2516	42	0	1
T2	4298	45	0	1
T3	2087	0	0	0
T4	451	0	0	0
T5	12250	0	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T38	0	3	0	1
T42	0	3	0	1
T43	0	46	0	1
T45	0	3	0	1
T76	0	3	0	1
T78	0	4	0	0
T79	0	4	0	0
T80	0	4	0	0
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	5052	0	109
T5	12250	0	0	0
T11	2336	4	0	1
T12	2053	0	0	0
T13	2511	62	0	1
T14	0	13	0	1
T22	1203	0	0	0
T23	4645	0	0	0
T37	3398	23	0	1
T38	0	43	0	1
T39	5002	0	0	0
T40	0	3	0	1
T43	0	3	0	1
T47	1313	0	0	0
T55	1560	0	0	0
T76	0	39	0	1
T84	0	4	0	0
T85	0	807	0	1
T86	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	1572	0	92
T6	250596	0	0	0
T13	2511	15	0	1
T14	2797	0	0	0
T20	0	1	0	0
T23	4645	0	0	0
T35	691058	0	0	0
T38	0	9	0	1
T39	5002	3	0	1
T40	0	3	0	1
T41	953	0	0	0
T42	0	0	0	1
T43	0	3	0	1
T44	0	8	0	1
T46	2509	0	0	0
T64	1200	0	0	0
T68	2129	0	0	0
T74	0	4	0	0
T76	0	6	0	1
T85	0	33	0	1
T87	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	574618	0	306
T1	2516	23	0	0
T2	4298	15	0	0
T3	2087	365	0	0
T4	451	155	0	0
T5	12250	873	0	0
T6	0	0	0	2
T10	3140	176	0	0
T11	2336	185	0	0
T12	2053	188	0	0
T20	0	0	0	2
T21	1153	16	0	0
T22	1203	1104	0	2
T35	0	0	0	2
T36	0	0	0	2
T47	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	2608	0	88
T6	250596	0	0	0
T13	2511	0	0	0
T14	2797	51	0	1
T23	4645	0	0	0
T37	3398	7	0	1
T38	0	35	0	1
T39	5002	0	0	0
T41	953	3	0	1
T42	0	3	0	1
T43	0	18	0	1
T45	0	0	0	1
T55	1560	0	0	0
T64	1200	0	0	0
T68	2129	0	0	0
T75	0	4	0	0
T76	0	3	0	1
T88	0	4	0	1
T89	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	137972	0	0
T4	451	224	0	0
T5	12250	0	0	0
T7	0	212	0	0
T8	0	630	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18686	0	0
T17	0	389	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	302	0	0
T55	1560	0	0	0
T70	0	652	0	0
T71	0	508	0	0
T72	0	1112	0	0
T73	0	1127	0	0