Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207620474	9291698	0	0
boot_gen_cmd_rd_A	207620474	32484	0	0
boot_ins_cmd_rd_A	207620474	36843	0	0
ctrl_rd_A	207620474	31926	0	0
err_code_test_rd_A	207620474	35945	0	0
intr_enable_rd_A	207620474	37901	0	0
max_num_reqs_between_reseeds_rd_A	207620474	32454	0	0
regwen_rd_A	207620474	38422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	9291698	0	0
T6	250596	95981	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	28655	0	0
T36	213371	123927	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T65	0	293213	0	0
T66	0	47143	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T97	0	146212	0	0
T212	0	200105	0	0
T213	0	97454	0	0
T214	0	57486	0	0
T215	0	301843	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	32484	0	0
T6	250596	1516	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2463	0	0
T217	0	5747	0	0
T218	0	2157	0	0
T219	0	1589	0	0
T220	0	958	0	0
T221	0	2719	0	0
T222	0	1663	0	0
T223	0	6582	0	0
T224	0	967	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	36843	0	0
T6	250596	1798	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2951	0	0
T217	0	6536	0	0
T218	0	2497	0	0
T219	0	1709	0	0
T220	0	1235	0	0
T221	0	3010	0	0
T222	0	1782	0	0
T223	0	6918	0	0
T224	0	1245	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	31926	0	0
T6	250596	1612	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T189	0	1	0	0
T216	0	2524	0	0
T217	0	5613	0	0
T218	0	2097	0	0
T225	0	1	0	0
T226	0	9	0	0
T227	0	2	0	0
T228	0	3	0	0
T229	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	35945	0	0
T6	250596	1632	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2541	0	0
T217	0	6192	0	0
T218	0	2156	0	0
T219	0	1622	0	0
T220	0	1186	0	0
T221	0	3208	0	0
T222	0	1981	0	0
T223	0	7193	0	0
T224	0	1137	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	37901	0	0
T6	250596	1535	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2693	0	0
T217	0	5787	0	0
T218	0	2242	0	0
T219	0	2155	0	0
T229	0	31	0	0
T230	0	17	0	0
T231	0	11	0	0
T232	0	33	0	0
T233	0	51	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	32454	0	0
T6	250596	1467	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2383	0	0
T217	0	5695	0	0
T218	0	2109	0	0
T219	0	1534	0	0
T220	0	1062	0	0
T221	0	2551	0	0
T222	0	1408	0	0
T223	0	6104	0	0
T224	0	946	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207620474	38422	0	0
T6	250596	1801	0	0
T14	2797	0	0	0
T20	2053	0	0	0
T35	691058	0	0	0
T36	213371	0	0	0
T40	1825	0	0	0
T44	2404	0	0	0
T46	2509	0	0	0
T68	2129	0	0	0
T69	2622	0	0	0
T216	0	2749	0	0
T217	0	6597	0	0
T218	0	2319	0	0
T219	0	1983	0	0
T220	0	1218	0	0
T221	0	3251	0	0
T222	0	1713	0	0
T223	0	7390	0	0
T224	0	1280	0	0