Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.25	93.91	97.07	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.66	82.84	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T14,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T16
1	0	Covered	T3,T11,T12

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T23,T4,T7	Yes	T23,T4,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T21,T22	Yes	T1,T21,T22	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T21	Yes	T3,T21,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T21	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T21,T22	Yes	T3,T21,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T7,T39,T40	Yes	T7,T39,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T23,T8,T12	Yes	T23,T8,T12	INPUT
edn_i[3].edn_req	Yes	Yes	T23,T8,T40	Yes	T23,T8,T40	INPUT
edn_i[4].edn_req	Yes	Yes	T24,T8,T17	Yes	T24,T8,T17	INPUT
edn_i[5].edn_req	Yes	Yes	T23,T18,T19	Yes	T23,T18,T19	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T11,T41	Yes	T2,T11,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T22,T23,T4	Yes	T21,T22,T23	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T22,T4	Yes	T3,T21,T22	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T7,T39,T40	Yes	T7,T39,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T39,T40,T18	Yes	T39,T40,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T7,T39,T40	Yes	T7,T39,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T23,T8,T20	Yes	T23,T8,T20	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T20,T9,T43	Yes	T23,T8,T20	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T8,T20	Yes	T23,T8,T20	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T23,T8,T40	Yes	T23,T8,T40	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T23,T8,T40	Yes	T23,T8,T40	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T23,T8,T40	Yes	T23,T8,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T24,T8,T44	Yes	T24,T8,T17	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T8,T45,T46	Yes	T24,T8,T17	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T24,T8,T17	Yes	T24,T8,T17	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T18,T19,T47	Yes	T23,T18,T19	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T5,T48,T49	Yes	T18,T50,T47	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T18,T19	Yes	T23,T18,T19	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T41,T51	Yes	T2,T41,T51	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T18,T50,T44	Yes	T2,T41,T18	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T41,T51	Yes	T2,T41,T51	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T22,T23,T4	Yes	T22,T23,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T22,T23,T4	Yes	T23,T4,T25	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T21	Yes	T2,T3,T21	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T7,T51,T52	Yes	T7,T51,T52	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T7,T14,T29	Yes	T7,T14,T29	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T11,T12	Yes	T3,T11,T12	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T7,T14,T29	Yes	T7,T14,T29	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T11,T12	Yes	T3,T11,T12	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	222204135	222017385	0	0
CsrngAppIfOut_A	222204135	222017385	0	0
FpvSecCmCntAlertCheck_A	222204135	119	0	0
FpvSecCmGenCmdFifoRptrCheck_A	222204135	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	222204135	80	0	0
FpvSecCmMainFsmCheck_A	222204135	80	0	0
FpvSecCmRegWeOnehotCheck_A	222204135	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	222204135	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	222204135	80	0	0
IntrEdnCmdReqDoneKnownO_A	222204135	222017385	0	0
TlAReadyKnownO_A	222204135	222017385	0	0
TlDValidKnownO_A	222204135	222017385	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	222204135	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[0].EdnDataStable_A	222204135	21852	0	428
gen_edn_if_asserts[0].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[1].EdnDataStable_A	222204135	5207	0	126
gen_edn_if_asserts[1].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[2].EdnDataStable_A	222204135	2897	0	122
gen_edn_if_asserts[2].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[3].EdnDataStable_A	222204135	53153	0	108
gen_edn_if_asserts[3].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[4].EdnDataStable_A	222204135	2183	0	111
gen_edn_if_asserts[4].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[5].EdnDataStable_A	222204135	3512	0	95
gen_edn_if_asserts[5].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	222204135	156119	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	222204135	568748	0	310
gen_edn_if_asserts[6].EdnDataStable_A	222204135	4826	0	90
gen_edn_if_asserts[6].EdnEndPointOut_A	222204135	222017385	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	222204135	156119	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	119	0	0
T11	1632	1	0	0
T12	0	1	0	0
T13	0	10	0	0
T14	2020	0	0	0
T29	2281	0	0	0
T37	938496	0	0	0
T39	5483	0	0	0
T40	3435	0	0	0
T41	2952	0	0	0
T51	2688	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	18010	0	0	0
T61	3031	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	80	0	0
T5	1269	0	0	0
T13	23182	10	0	0
T15	0	20	0	0
T16	0	20	0	0
T45	4020	0	0	0
T62	0	20	0	0
T63	0	10	0	0
T64	1521	0	0	0
T65	781	0	0	0
T66	2164	0	0	0
T67	1585	0	0	0
T68	3720	0	0	0
T69	524649	0	0	0
T70	3492	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	21852	0	428
T4	261769	141	0	0
T7	2507	0	0	0
T8	4198	19	0	1
T11	1632	0	0	0
T14	0	8	0	1
T21	1994	3	0	1
T22	2035	23	0	1
T23	1620	19	0	1
T24	1151	0	0	0
T25	18033	10	0	0
T29	0	8	0	1
T37	0	0	0	1
T39	0	0	0	1
T60	0	6	0	1
T76	1958	28	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	5207	0	126
T7	2507	4	0	1
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T18	0	13	0	1
T29	2281	0	0	0
T37	938496	0	0	0
T39	0	42	0	1
T40	0	55	0	1
T41	2952	0	0	0
T42	0	3	0	1
T44	0	19	0	1
T45	0	0	0	1
T50	0	39	0	1
T51	2688	0	0	0
T60	18010	0	0	0
T73	0	4	0	0
T76	1958	0	0	0
T81	0	4	0	0
T82	0	4	0	1
T83	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	2897	0	122
T4	261769	0	0	0
T7	2507	0	0	0
T8	4198	3	0	1
T9	0	46	0	1
T11	1632	0	0	0
T14	2020	0	0	0
T18	0	5	0	1
T20	0	4	0	0
T23	1620	3	0	1
T24	1151	0	0	0
T25	18033	0	0	0
T43	0	36	0	1
T44	0	3	0	1
T60	18010	0	0	0
T76	1958	0	0	0
T84	0	4	0	1
T85	0	4	0	1
T86	0	4	0	1
T87	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	53153	0	108
T4	261769	0	0	0
T7	2507	0	0	0
T8	4198	21	0	1
T9	0	36	0	1
T11	1632	0	0	0
T14	2020	0	0	0
T17	0	15	0	1
T18	0	15	0	1
T23	1620	21	0	1
T24	1151	0	0	0
T25	18033	0	0	0
T40	0	32	0	1
T44	0	3	0	1
T46	0	0	0	1
T60	18010	0	0	0
T65	0	4	0	0
T75	0	4	0	0
T76	1958	0	0	0
T88	0	4	0	1
T89	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	2183	0	111
T7	2507	0	0	0
T8	4198	26	0	1
T11	1632	0	0	0
T14	2020	0	0	0
T17	0	3	0	1
T24	1151	3	0	1
T25	18033	0	0	0
T29	2281	0	0	0
T41	2952	0	0	0
T42	0	3	0	1
T44	0	3	0	1
T45	0	12	0	1
T46	0	52	0	1
T48	0	0	0	1
T60	18010	0	0	0
T76	1958	0	0	0
T90	0	4	0	1
T91	0	4	0	0
T92	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	3512	0	95
T4	261769	0	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T18	0	3	0	1
T19	0	4	0	0
T23	1620	3	0	1
T24	1151	0	0	0
T25	18033	0	0	0
T44	0	12	0	1
T45	0	3	0	1
T46	0	0	0	1
T47	0	4	0	0
T48	0	0	0	1
T50	0	3	0	1
T60	18010	0	0	0
T76	1958	0	0	0
T93	0	4	0	1
T94	0	3	0	1
T95	0	4	0	0
T96	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	568748	0	310
T1	5810	71	0	0
T2	1104	63	0	0
T3	1260	801	0	0
T4	261769	2843	0	2
T7	2507	138	0	0
T19	0	0	0	2
T21	1994	24	0	0
T22	2035	41	0	0
T23	1620	16	0	0
T24	1151	80	0	0
T25	18033	3495	0	2
T38	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	4826	0	90
T2	1104	3	0	1
T3	1260	0	0	0
T4	261769	0	0	0
T7	2507	0	0	0
T18	0	18	0	1
T19	0	1	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T41	0	4	0	1
T44	0	15	0	1
T48	0	0	0	1
T49	0	0	0	1
T50	0	22	0	1
T51	0	4	0	1
T76	1958	0	0	0
T97	0	4	0	0
T98	0	4	0	1
T99	0	32	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	156119	0	0
T3	1260	377	0	0
T4	261769	0	0	0
T5	0	592	0	0
T6	0	646	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	324	0	0
T12	0	484	0	0
T13	0	7686	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1167	0	0
T78	0	340	0	0
T79	0	1106	0	0
T80	0	253	0	0