Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	222718358	9710590	0	0
boot_gen_cmd_rd_A	222718358	58140	0	0
boot_ins_cmd_rd_A	222718358	65248	0	0
ctrl_rd_A	222718358	57964	0	0
err_code_test_rd_A	222718358	64367	0	0
intr_enable_rd_A	222718358	67041	0	0
max_num_reqs_between_reseeds_rd_A	222718358	57308	0	0
regwen_rd_A	222718358	65752	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	9710590	0	0
T4	261769	91869	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T37	0	533445	0	0
T38	0	102044	0	0
T60	18010	0	0	0
T69	0	205891	0	0
T71	0	106393	0	0
T76	1958	0	0	0
T178	0	324874	0	0
T211	0	154878	0	0
T212	0	158540	0	0
T213	0	109249	0	0
T214	0	68966	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	58140	0	0
T4	261769	2501	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	3211	0	0
T60	18010	0	0	0
T71	0	3318	0	0
T76	1958	0	0	0
T212	0	4988	0	0
T215	0	3232	0	0
T216	0	1548	0	0
T217	0	6670	0	0
T218	0	2627	0	0
T219	0	7051	0	0
T220	0	4809	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	65248	0	0
T4	261769	3208	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	3442	0	0
T60	18010	0	0	0
T71	0	3511	0	0
T76	1958	0	0	0
T212	0	5183	0	0
T215	0	4150	0	0
T216	0	1552	0	0
T217	0	7524	0	0
T218	0	2918	0	0
T219	0	8289	0	0
T220	0	5319	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	57964	0	0
T4	261769	2922	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T27	0	7	0	0
T29	2281	0	0	0
T38	0	2751	0	0
T60	18010	0	0	0
T71	0	3037	0	0
T76	1958	0	0	0
T84	0	2	0	0
T163	0	9	0	0
T212	0	4961	0	0
T215	0	3263	0	0
T221	0	7	0	0
T222	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	64367	0	0
T4	261769	3035	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	3331	0	0
T60	18010	0	0	0
T71	0	3790	0	0
T76	1958	0	0	0
T212	0	5254	0	0
T215	0	3613	0	0
T216	0	1514	0	0
T217	0	7912	0	0
T218	0	2898	0	0
T219	0	7942	0	0
T220	0	5250	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	67041	0	0
T4	261769	3297	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	2949	0	0
T60	18010	22	0	0
T71	0	3929	0	0
T76	1958	0	0	0
T177	0	26	0	0
T179	0	17	0	0
T212	0	5414	0	0
T215	0	3778	0	0
T223	0	12	0	0
T224	0	40	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	57308	0	0
T4	261769	2412	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	3012	0	0
T60	18010	0	0	0
T71	0	3291	0	0
T76	1958	0	0	0
T212	0	4593	0	0
T215	0	3250	0	0
T216	0	1420	0	0
T217	0	6840	0	0
T218	0	2511	0	0
T219	0	7004	0	0
T220	0	4666	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222718358	65752	0	0
T4	261769	2794	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	1632	0	0	0
T14	2020	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T29	2281	0	0	0
T38	0	3440	0	0
T60	18010	0	0	0
T71	0	3456	0	0
T76	1958	0	0	0
T212	0	5292	0	0
T215	0	3577	0	0
T216	0	1636	0	0
T217	0	7550	0	0
T218	0	3113	0	0
T219	0	7895	0	0
T220	0	5400	0	0