Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg

Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.24	95.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_hw_cmd_sts_cg	95.24	1	100	1	64	64

---

Group Instance : edn_hw_cmd_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

---

Summary for Group Instance edn_hw_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	1	15	93.75
Crosses	5	0	5	100.00

Variables for Group Instance edn_hw_cmd_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acmd	4	0	4	100.00	100	1	1	0
cp_auto_mode	2	0	2	100.00	100	1	1	0
cp_boot_mode	2	0	2	100.00	100	1	1	0
cp_cmd_ack	2	0	2	100.00	100	1	1	0
cp_cmd_sts	6	1	5	83.33	100	1	1	0

Crosses for Group Instance edn_hw_cmd_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_acmd_boot_mode	3	0	3	100.00	100	1	1	0
cr_acmd_auto_mode	2	0	2	100.00	100	1	1	0

Summary for Variable cp_acmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_acmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[INV]	0	Excluded
auto[UPD]	0	Excluded
auto[GENB]	0	Excluded
auto[GENU]	0	Excluded
unused	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[INS]	71	1			T26	2		T28	1		T62	2
auto[RES]	14	1			T9	1		T221	1		T156	1
auto[GEN]	89	1			T8	1		T52	1		T94	1
auto[UNI]	6	1			T21	1		T220	1		T309	1

---

Summary for Variable cp_auto_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_auto_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_auto_mode

344

1

T2

2

T26

2

T8

1

auto_mode

56

1

T8

1

T9

1

T52

1

---

Summary for Variable cp_boot_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_boot_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_boot_mode

276

1

T2

2

T8

2

T28

1

boot_mode

124

1

T26

2

T28

1

T21

1

---

Summary for Variable cp_cmd_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

no_ack

215

1

T8

1

T28

1

T9

1

ack

185

1

T2

2

T26

2

T8

1

---

Summary for Variable cp_cmd_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	6	1	5	83.33

Automatically Generated Bins for cp_cmd_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[CMD_STS_UNDRIVEN]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CMD_STS_SUCCESS]	222	1			T8	1		T28	1		T9	1
auto[CMD_STS_INVALID_ACMD]	34	1			T28	1		T86	1		T91	1
auto[CMD_STS_INVALID_GEN_CMD]	49	1			T8	1		T69	1		T125	1
auto[CMD_STS_INVALID_CMD_SEQ]	56	1			T2	2		T62	1		T55	1
auto[CMD_STS_RESEED_CNT_EXCEEDED]	39	1			T26	2		T9	1		T21	1

---

Summary for Cross cr_acmd_boot_mode

Samples crossed: cp_acmd cp_boot_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	3	0	3	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins

cp_acmd	cp_boot_mode	COUNT	STATUS
[auto[INV]]	[not_boot_mode , boot_mode]	--	Excluded	(2 bins)
[auto[UPD]]	[not_boot_mode , boot_mode]	--	Excluded	(2 bins)
[auto[GENB] , auto[GENU]]	[not_boot_mode , boot_mode]	--	Excluded	(4 bins)

Covered bins

cp_acmd

cp_boot_mode

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

boot_mode

71

1

T26

2

T28

1

T62

2

auto[GEN]

boot_mode

47

1

T91

1

T104

1

T69

1

auto[UNI]

boot_mode

6

1

T21

1

T220

1

T309

1

User Defined Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
not_boot_mode	0	Excluded
not_valid_boot_commands	0	Excluded

---

Summary for Cross cr_acmd_auto_mode

Samples crossed: cp_acmd cp_auto_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins

cp_acmd	cp_auto_mode	COUNT	STATUS
[auto[INV]]	[not_auto_mode , auto_mode]	--	Excluded	(2 bins)
[auto[UPD]]	[not_auto_mode , auto_mode]	--	Excluded	(2 bins)
[auto[GENB] , auto[GENU]]	[not_auto_mode , auto_mode]	--	Excluded	(4 bins)

Covered bins

cp_acmd

cp_auto_mode

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[RES]

auto_mode

14

1

T9

1

T221

1

T156

1

auto[GEN]

auto_mode

42

1

T8

1

T52

1

T94

1

User Defined Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
not_auto_mode	0	Excluded
not_valid_boot_commands	0	Excluded