Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	711110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5811224

1

T1

11

T2

21

T3

41229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1715836	1			T1	4		T2	29		T3	12278
values[0x0]	2219312	1			T1	7		T2	9		T3	15744
values[0x1]	2587186	1			T1	8		T2	14		T3	18584

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6174325

1

T1

13

T2

32

T3

43971

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24511	1			T2	1		T3	167		T4	391
valid_sources[0x01]	24551	1			T2	1		T3	173		T10	3
valid_sources[0x02]	25390	1			T3	195		T4	371		T45	728
valid_sources[0x03]	25726	1			T3	182		T10	1		T4	402
valid_sources[0x04]	26221	1			T3	186		T4	403		T45	884
valid_sources[0x05]	23686	1			T2	1		T3	187		T10	1
valid_sources[0x06]	25477	1			T3	180		T10	3		T4	389
valid_sources[0x07]	25676	1			T2	1		T3	190		T4	401
valid_sources[0x08]	25247	1			T2	2		T3	167		T4	432
valid_sources[0x09]	24652	1			T3	184		T4	420		T45	843
valid_sources[0x0a]	25179	1			T3	199		T28	2		T29	3
valid_sources[0x0b]	25459	1			T2	1		T3	199		T4	390
valid_sources[0x0c]	25010	1			T3	154		T4	428		T45	955
valid_sources[0x0d]	24738	1			T3	181		T4	430		T45	1052
valid_sources[0x0e]	25416	1			T3	194		T4	392		T45	759
valid_sources[0x0f]	27147	1			T3	152		T4	351		T45	873
valid_sources[0x10]	24670	1			T3	175		T4	368		T45	1008
valid_sources[0x11]	24013	1			T3	187		T4	366		T45	764
valid_sources[0x12]	24059	1			T2	1		T3	169		T10	2
valid_sources[0x13]	25755	1			T3	159		T26	5		T4	415
valid_sources[0x14]	25114	1			T3	167		T4	373		T45	832
valid_sources[0x15]	26028	1			T3	175		T10	1		T4	398
valid_sources[0x16]	25147	1			T2	1		T3	174		T28	3
valid_sources[0x17]	25562	1			T3	164		T4	364		T45	733
valid_sources[0x18]	24078	1			T3	200		T26	1		T4	395
valid_sources[0x19]	26770	1			T3	166		T4	427		T45	1019
valid_sources[0x1a]	26679	1			T3	183		T4	437		T45	930
valid_sources[0x1b]	25197	1			T2	2		T3	203		T4	384
valid_sources[0x1c]	25084	1			T2	2		T3	192		T26	1
valid_sources[0x1d]	22528	1			T2	1		T3	190		T4	370
valid_sources[0x1e]	26785	1			T3	184		T28	1		T10	2
valid_sources[0x1f]	23497	1			T3	177		T4	440		T45	1009
valid_sources[0x20]	24723	1			T3	175		T4	428		T45	778
valid_sources[0x21]	28149	1			T3	181		T4	408		T45	1163
valid_sources[0x22]	25221	1			T3	187		T4	379		T45	964
valid_sources[0x23]	25473	1			T2	1		T3	181		T4	385
valid_sources[0x24]	26541	1			T3	182		T10	2		T4	401
valid_sources[0x25]	24075	1			T3	180		T4	401		T45	907
valid_sources[0x26]	26598	1			T3	165		T30	1		T10	3
valid_sources[0x27]	25083	1			T2	1		T3	185		T10	1
valid_sources[0x28]	26743	1			T3	175		T4	399		T45	881
valid_sources[0x29]	25403	1			T2	1		T3	182		T4	390
valid_sources[0x2a]	26487	1			T3	179		T28	5		T10	1
valid_sources[0x2b]	25135	1			T3	173		T4	377		T45	941
valid_sources[0x2c]	24897	1			T3	186		T4	414		T45	961
valid_sources[0x2d]	24897	1			T3	200		T26	1		T10	1
valid_sources[0x2e]	27308	1			T3	191		T28	9		T10	2
valid_sources[0x2f]	25525	1			T3	193		T4	414		T45	849
valid_sources[0x30]	25084	1			T3	195		T26	1		T4	404
valid_sources[0x31]	26568	1			T3	179		T29	21		T4	381
valid_sources[0x32]	26068	1			T3	174		T4	407		T45	1057
valid_sources[0x33]	25554	1			T1	1		T3	180		T4	375
valid_sources[0x34]	25245	1			T3	176		T4	410		T45	842
valid_sources[0x35]	25883	1			T3	190		T4	355		T45	876
valid_sources[0x36]	25856	1			T3	195		T10	1		T4	401
valid_sources[0x37]	24525	1			T3	152		T10	1		T4	362
valid_sources[0x38]	27431	1			T3	182		T10	1		T4	423
valid_sources[0x39]	25298	1			T3	174		T28	3		T30	1
valid_sources[0x3a]	24766	1			T3	198		T8	36		T10	2
valid_sources[0x3b]	25408	1			T3	184		T28	2		T4	383
valid_sources[0x3c]	24298	1			T3	178		T30	1		T4	374
valid_sources[0x3d]	25662	1			T3	155		T4	398		T45	1001
valid_sources[0x3e]	26456	1			T3	169		T29	2		T4	413
valid_sources[0x3f]	24783	1			T3	193		T4	380		T45	1032
valid_sources[0x40]	24492	1			T3	173		T29	7		T10	2
valid_sources[0x41]	25284	1			T2	1		T3	185		T26	2
valid_sources[0x42]	25597	1			T3	173		T8	3		T4	380
valid_sources[0x43]	24963	1			T2	1		T3	190		T4	389
valid_sources[0x44]	25152	1			T3	149		T28	6		T4	366
valid_sources[0x45]	25555	1			T3	191		T28	1		T4	377
valid_sources[0x46]	25647	1			T3	174		T9	40		T4	370
valid_sources[0x47]	26316	1			T3	206		T4	357		T45	912
valid_sources[0x48]	26127	1			T3	187		T4	400		T45	1023
valid_sources[0x49]	25417	1			T3	206		T10	2		T4	386
valid_sources[0x4a]	24854	1			T3	192		T26	2		T4	363
valid_sources[0x4b]	24551	1			T3	197		T4	370		T45	887
valid_sources[0x4c]	24173	1			T1	2		T3	183		T4	357
valid_sources[0x4d]	25076	1			T3	191		T4	368		T45	801
valid_sources[0x4e]	24798	1			T3	182		T4	385		T45	722
valid_sources[0x4f]	25567	1			T3	171		T10	1		T4	363
valid_sources[0x50]	26032	1			T3	190		T4	410		T45	950
valid_sources[0x51]	24472	1			T3	155		T28	1		T4	387
valid_sources[0x52]	27654	1			T1	1		T3	181		T4	428
valid_sources[0x53]	26598	1			T3	198		T4	367		T45	857
valid_sources[0x54]	27112	1			T3	174		T8	14		T4	381
valid_sources[0x55]	25220	1			T3	178		T10	1		T4	392
valid_sources[0x56]	24542	1			T3	173		T4	382		T45	862
valid_sources[0x57]	24581	1			T2	1		T3	181		T4	405
valid_sources[0x58]	25205	1			T3	183		T4	381		T45	801
valid_sources[0x59]	27486	1			T3	169		T4	369		T45	1112
valid_sources[0x5a]	24842	1			T3	210		T4	382		T45	890
valid_sources[0x5b]	25443	1			T2	1		T3	171		T26	1
valid_sources[0x5c]	27926	1			T3	206		T10	1		T4	356
valid_sources[0x5d]	25649	1			T3	166		T10	1		T4	433
valid_sources[0x5e]	25608	1			T3	173		T4	378		T45	1112
valid_sources[0x5f]	24769	1			T3	181		T10	1		T4	400
valid_sources[0x60]	26167	1			T2	1		T3	190		T4	422
valid_sources[0x61]	25361	1			T3	192		T4	399		T45	1080
valid_sources[0x62]	27041	1			T3	197		T10	2		T4	397
valid_sources[0x63]	25948	1			T3	172		T10	4		T4	396
valid_sources[0x64]	25647	1			T3	174		T4	461		T45	952
valid_sources[0x65]	26045	1			T3	180		T10	1		T4	386
valid_sources[0x66]	24971	1			T3	196		T26	1		T29	3
valid_sources[0x67]	25744	1			T3	182		T4	408		T45	850
valid_sources[0x68]	26063	1			T3	192		T26	2		T4	395
valid_sources[0x69]	25404	1			T3	201		T26	5		T10	1
valid_sources[0x6a]	24801	1			T3	190		T4	375		T45	899
valid_sources[0x6b]	25735	1			T3	208		T4	394		T45	834
valid_sources[0x6c]	24978	1			T3	172		T28	1		T4	381
valid_sources[0x6d]	25082	1			T3	208		T29	25		T30	1
valid_sources[0x6e]	25552	1			T3	195		T30	2		T4	362
valid_sources[0x6f]	25596	1			T3	175		T10	2		T4	392
valid_sources[0x70]	25634	1			T3	182		T4	412		T45	938
valid_sources[0x71]	24200	1			T2	2		T3	215		T10	1
valid_sources[0x72]	26578	1			T3	176		T28	4		T10	1
valid_sources[0x73]	25300	1			T3	187		T10	1		T4	416
valid_sources[0x74]	25533	1			T3	187		T26	3		T4	409
valid_sources[0x75]	24317	1			T1	1		T3	185		T4	389
valid_sources[0x76]	25940	1			T3	196		T4	384		T45	773
valid_sources[0x77]	25871	1			T3	173		T28	4		T4	378
valid_sources[0x78]	25951	1			T3	174		T4	391		T45	954
valid_sources[0x79]	24884	1			T3	179		T4	393		T45	889
valid_sources[0x7a]	24672	1			T3	179		T26	1		T30	1
valid_sources[0x7b]	23115	1			T1	2		T3	154		T8	3
valid_sources[0x7c]	26604	1			T3	179		T4	383		T45	788
valid_sources[0x7d]	25904	1			T3	185		T8	13		T10	1
valid_sources[0x7e]	25372	1			T3	164		T10	2		T4	448
valid_sources[0x7f]	26727	1			T3	187		T4	415		T45	884
valid_sources[0x80]	24165	1			T3	185		T4	389		T45	922

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1463465

1

T1

2

T2

6

T3

10394

values[0x0]

all_enables

biggest_size

2173606

1

T1

5

T2

7

T3

15369

values[0x1]

all_enables

biggest_size

2174153

1

T1

4

T2

8

T3

15466