Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2679	1			T3	24		T29	1		T10	5
non_zero_bins[1]	2014	1			T3	15		T29	1		T10	2
zero	9601	1			T1	5		T2	6		T3	103

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	502	1			T3	7		T4	11		T45	7
uni	3817	1			T2	1		T3	45		T29	1
gen	4534	1			T1	2		T2	3		T3	40
res	854	1			T3	5		T29	1		T9	1
ins	4587	1			T1	3		T2	2		T3	45

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9542

1

T2

2

T3

108

T26

1

mubi_true

4752

1

T1

5

T2

4

T3

34

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

19

1

T156

1

T294

1

T295

1

pass

14275

1

T1

5

T2

6

T3

142

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	118	1			T3	2		T4	2		T45	2
upd	non_zero_bins[0]	pass	mubi_true	110	1			T3	1		T4	3		T45	2
upd	non_zero_bins[1]	pass	mubi_false	88	1			T45	2		T71	4		T296	1
upd	non_zero_bins[1]	pass	mubi_true	91	1			T3	1		T4	2		T297	1
upd	zero	pass	mubi_false	51	1			T4	3		T71	3		T59	1
upd	zero	pass	mubi_true	44	1			T3	3		T4	1		T45	1
uni	zero	pass	mubi_false	2815	1			T2	1		T3	36		T29	1
uni	zero	pass	mubi_true	1002	1			T3	9		T4	17		T45	23
gen	non_zero_bins[0]	pass	mubi_false	537	1			T3	6		T29	1		T10	3
gen	non_zero_bins[0]	pass	mubi_true	485	1			T3	5		T10	1		T4	10
gen	non_zero_bins[1]	pass	mubi_false	401	1			T3	3		T4	3		T45	9
gen	non_zero_bins[1]	pass	mubi_true	354	1			T3	1		T4	8		T45	3
gen	zero	fail	mubi_false	16	1			T294	1		T295	1		T298	1
gen	zero	pass	mubi_false	1997	1			T2	1		T3	24		T8	1
gen	zero	pass	mubi_true	744	1			T1	2		T2	2		T3	1
res	non_zero_bins[0]	pass	mubi_false	202	1			T4	2		T45	2		T22	3
res	non_zero_bins[0]	pass	mubi_true	171	1			T4	3		T45	1		T85	1
res	non_zero_bins[1]	pass	mubi_false	146	1			T3	2		T10	2		T45	1
res	non_zero_bins[1]	pass	mubi_true	135	1			T3	2		T29	1		T20	1
res	zero	fail	mubi_false	3	1			T156	1		T157	1		T299	1
res	zero	pass	mubi_false	110	1			T3	1		T9	1		T4	2
res	zero	pass	mubi_true	87	1			T4	1		T45	1		T11	2
ins	non_zero_bins[0]	pass	mubi_false	543	1			T3	4		T4	5		T45	5
ins	non_zero_bins[0]	pass	mubi_true	513	1			T3	6		T10	1		T20	1
ins	non_zero_bins[1]	pass	mubi_false	418	1			T3	5		T4	7		T45	10
ins	non_zero_bins[1]	pass	mubi_true	381	1			T3	1		T4	8		T45	6
ins	zero	pass	mubi_false	2097	1			T3	25		T26	1		T8	1
ins	zero	pass	mubi_true	635	1			T1	3		T2	2		T3	4

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded