Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T40,T41
1	1	Covered	T1,T2,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T9,T20,T21
1	1	Covered	T8,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T26,T8
1	0	Covered	T1,T40,T41

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T26,T8
1	Covered	T1,T40,T41

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T26,T8
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T26
1	Covered	T1,T40,T41

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T26

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T8,T9,T10
AutoCaptGenCnt	143	Covered	T8,T9,T10
AutoCaptReseedCnt	141	Covered	T9,T10,T20
AutoDispatch	125	Covered	T8,T9,T10
AutoFirstAckWait	119	Covered	T8,T9,T10
AutoLoadIns	69	Covered	T8,T9,T10
AutoSendGenCmd	150	Covered	T8,T9,T10
AutoSendReseedCmd	162	Covered	T9,T10,T20
BootDone	98	Covered	T1,T2,T28
BootGenAckWait	90	Covered	T1,T2,T28
BootInsAckWait	80	Covered	T1,T2,T26
BootLoadGen	85	Covered	T1,T2,T28
BootLoadIns	65	Covered	T1,T2,T26
BootLoadUni	102	Covered	T2,T28,T21
BootPulse	94	Covered	T1,T2,T28
BootUniAckWait	107	Covered	T2,T28,T21
Error	188	Covered	T1,T40,T41
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T26,T8
SWPortMode	74	Covered	T2,T3,T26

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T20
AutoAckWait->Error	188	Covered	T119
AutoAckWait->Idle	211	Covered	T20,T22,T23
AutoAckWait->RejectCsrngEntropy	188	Covered	T8,T9,T94
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T8,T9,T10
AutoCaptGenCnt->Error	188	Covered	T120,T121
AutoCaptGenCnt->Idle	211	Covered	T122,T123,T124
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T100,T125,T126
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T20
AutoCaptReseedCnt->Error	188	Covered	T127
AutoCaptReseedCnt->Idle	211	Covered	T97,T128,T129
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T52,T130,T131
AutoDispatch->AutoCaptGenCnt	143	Covered	T8,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T20
AutoDispatch->Error	188	Covered	T132
AutoDispatch->Idle	138	Covered	T10,T20,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T133
AutoFirstAckWait->AutoDispatch	125	Covered	T8,T9,T10
AutoFirstAckWait->Error	188	Covered	T134
AutoFirstAckWait->Idle	211	Covered	T135,T136,T137
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T51,T138,T139
AutoLoadIns->AutoFirstAckWait	119	Covered	T8,T9,T10
AutoLoadIns->Error	188	Covered	T112,T140,T141
AutoLoadIns->Idle	211	Covered	T8,T22,T5
AutoLoadIns->RejectCsrngEntropy	188	Covered	T142,T143,T144
AutoSendGenCmd->AutoAckWait	156	Covered	T8,T9,T10
AutoSendGenCmd->Error	188	Covered	T145,T146,T147
AutoSendGenCmd->Idle	211	Covered	T23,T148,T149
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T101,T150,T151
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T20
AutoSendReseedCmd->Error	188	Covered	T115,T152,T153
AutoSendReseedCmd->Idle	211	Covered	T154,T155
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T156,T157,T158
BootDone->BootLoadUni	102	Covered	T2,T28,T21
BootDone->Error	188	Covered	T14,T67,T159
BootDone->Idle	211	Covered	T95,T160,T161
BootDone->RejectCsrngEntropy	188	Covered	T91,T53,T162
BootGenAckWait->BootPulse	94	Covered	T1,T2,T28
BootGenAckWait->Error	188	Covered	T66,T77,T163
BootGenAckWait->Idle	211	Covered	T164,T58,T77
BootGenAckWait->RejectCsrngEntropy	188	Covered	T28,T62,T55
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T28
BootInsAckWait->Error	188	Covered	T165,T166,T167
BootInsAckWait->Idle	211	Covered	T1,T40,T41
BootInsAckWait->RejectCsrngEntropy	188	Covered	T26,T168,T169
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T28
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T54,T170,T171
BootLoadGen->RejectCsrngEntropy	188	Covered	T86,T172,T173
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T26
BootLoadIns->Error	188	Covered	T174,T175,T176
BootLoadIns->Idle	211	Covered	T90,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T2,T179,T180
BootLoadUni->BootUniAckWait	107	Covered	T2,T28,T21
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T181,T182,T183
BootPulse->BootDone	98	Covered	T1,T2,T28
BootPulse->Error	188	Covered	T40,T184,T171
BootPulse->Idle	211	Covered	T185,T186,T187
BootPulse->RejectCsrngEntropy	188	Covered	T188,T189,T190
BootUniAckWait->Error	188	Covered	T191
BootUniAckWait->Idle	112	Covered	T2,T28,T62
BootUniAckWait->RejectCsrngEntropy	188	Covered	T21,T104,T99
Idle->AutoLoadIns	69	Covered	T8,T9,T10
Idle->BootLoadIns	65	Covered	T1,T2,T26
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T8,T28,T9
Idle->SWPortMode	74	Covered	T2,T3,T26
RejectCsrngEntropy->Error	188	Covered	T65,T192,T193
RejectCsrngEntropy->Idle	211	Covered	T2,T26,T8
SWPortMode->Error	188	Covered	T88,T15,T16
SWPortMode->Idle	211	Covered	T3,T26,T9
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T26,T62

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T26
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T28
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T28
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T28
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T28
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T28,T21
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T28
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T28,T21
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T87,T46
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T28,T21
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T10,T20
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T20
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T20
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T20
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T26
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T8
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T40,T41
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T41,T5

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T40,T41
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T26,T8
0	-	-	1	Covered	T1,T2,T26
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	238436454	153412	0	0
FpvSecCmErrorStEscalate_A	238436454	154707	0	0
u_state_regs_A	238401209	238202740	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	153412	0	0
T1	1894	1010	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1020	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	352	0	0
T15	0	416	0	0
T16	0	885	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T40	0	990	0	0
T41	0	220	0	0
T68	0	1086	0	0
T88	0	422	0	0
T89	0	325	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	154707	0	0
T1	1894	1011	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1021	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	353	0	0
T15	0	417	0	0
T16	0	886	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T40	0	991	0	0
T41	0	221	0	0
T68	0	1087	0	0
T88	0	423	0	0
T89	0	326	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238401209	238202740	0	0
T1	1728	1561	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0