Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T44
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T39
1	0	1	Covered	T1,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476115268	1542929	0	0
DepthKnown_A	476872908	476475970	0	0
RvalidKnown_A	476872908	476475970	0	0
WreadyKnown_A	476872908	476475970	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	476457894	1617496	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476115268	1542929	0	0
T4	539136	0	0	0
T5	0	53	0	0
T8	4104	965	0	0
T9	3598	552	0	0
T10	4044	1391	0	0
T20	4354	1854	0	0
T21	0	83	0	0
T22	0	2059	0	0
T23	0	4877	0	0
T27	4424	0	0	0
T28	4648	0	0	0
T29	4632	0	0	0
T30	5874	0	0	0
T45	1348734	0	0	0
T51	0	533	0	0
T52	0	1099	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476872908	476475970	0	0
T1	3788	3454	0	0
T2	4208	4018	0	0
T3	389078	389060	0	0
T8	4104	4000	0	0
T9	3598	3436	0	0
T26	4800	4654	0	0
T27	4424	4238	0	0
T28	4648	4452	0	0
T29	4632	4446	0	0
T30	5874	5698	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476872908	476475970	0	0
T1	3788	3454	0	0
T2	4208	4018	0	0
T3	389078	389060	0	0
T8	4104	4000	0	0
T9	3598	3436	0	0
T26	4800	4654	0	0
T27	4424	4238	0	0
T28	4648	4452	0	0
T29	4632	4446	0	0
T30	5874	5698	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476872908	476475970	0	0
T1	3788	3454	0	0
T2	4208	4018	0	0
T3	389078	389060	0	0
T8	4104	4000	0	0
T9	3598	3436	0	0
T26	4800	4654	0	0
T27	4424	4238	0	0
T28	4648	4452	0	0
T29	4632	4446	0	0
T30	5874	5698	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	476457894	1617496	0	0
T1	3788	312	0	0
T2	4208	0	0	0
T3	389078	0	0	0
T8	4104	965	0	0
T9	3598	552	0	0
T10	0	1391	0	0
T20	0	1854	0	0
T21	0	83	0	0
T22	0	2059	0	0
T23	0	4877	0	0
T26	4800	0	0	0
T27	4424	0	0	0
T28	4648	0	0	0
T29	4632	0	0	0
T30	5874	0	0	0
T40	0	366	0	0
T51	0	533	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T107,T108
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T109
1	0	1	Covered	T1,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	238057634	765539	0	0
DepthKnown_A	238436454	238237985	0	0
RvalidKnown_A	238436454	238237985	0	0
WreadyKnown_A	238436454	238237985	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	238228947	802728	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238057634	765539	0	0
T4	269568	0	0	0
T5	0	15	0	0
T8	2052	435	0	0
T9	1799	274	0	0
T10	2022	678	0	0
T20	2177	912	0	0
T21	0	41	0	0
T22	0	1022	0	0
T23	0	2374	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T45	674367	0	0	0
T51	0	274	0	0
T52	0	538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	238228947	802728	0	0
T1	1894	157	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T8	2052	435	0	0
T9	1799	274	0	0
T10	0	678	0	0
T20	0	912	0	0
T21	0	41	0	0
T22	0	1022	0	0
T23	0	2374	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T40	0	184	0	0
T51	0	274	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T110
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T79,T111
1	0	1	Covered	T1,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	238057634	777390	0	0
DepthKnown_A	238436454	238237985	0	0
RvalidKnown_A	238436454	238237985	0	0
WreadyKnown_A	238436454	238237985	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	238228947	814768	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238057634	777390	0	0
T4	269568	0	0	0
T5	0	38	0	0
T8	2052	530	0	0
T9	1799	278	0	0
T10	2022	713	0	0
T20	2177	942	0	0
T21	0	42	0	0
T22	0	1037	0	0
T23	0	2503	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T45	674367	0	0	0
T51	0	259	0	0
T52	0	561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	238228947	814768	0	0
T1	1894	155	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T8	2052	530	0	0
T9	1799	278	0	0
T10	0	713	0	0
T20	0	942	0	0
T21	0	42	0	0
T22	0	1037	0	0
T23	0	2503	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T40	0	182	0	0
T51	0	259	0	0