Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.40	98.25	93.97	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.32	99.92	92.75	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T32,T33

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T5,T6,T39

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T25	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T4	Yes	T3,T10,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T25	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T25	INPUT
tl_i.a_address[31:0]	Yes	Yes	T3,T25,T10	Yes	T3,T25,T10	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T43,T44	Yes	T4,T43,T44	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T25	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T25	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T25,T10	Yes	T3,T25,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T28,T45,T46	Yes	T28,T45,T46	INPUT
edn_i[2].edn_req	Yes	Yes	T47,T45,T46	Yes	T47,T45,T46	INPUT
edn_i[3].edn_req	Yes	Yes	T45,T5,T35	Yes	T45,T5,T35	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T48,T49	Yes	T2,T48,T49	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T9,T50	Yes	T1,T9,T50	INPUT
edn_i[6].edn_req	Yes	Yes	T51,T52,T11	Yes	T51,T52,T11	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T25,T10	Yes	T3,T25,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T25,T26,T4	Yes	T25,T10,T26	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T25,T10	Yes	T3,T25,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T28,T45,T48	Yes	T28,T45,T46	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T28,T48,T21	Yes	T28,T45,T46	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T28,T45,T46	Yes	T28,T45,T46	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T45,T46,T32	Yes	T47,T45,T46	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T45,T46,T21	Yes	T45,T46,T32	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T47,T45,T46	Yes	T47,T45,T46	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T45,T53,T54	Yes	T45,T53,T54	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T45,T54,T55	Yes	T45,T54,T55	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T45,T5,T35	Yes	T45,T5,T35	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T48,T49,T11	Yes	T2,T48,T49	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T49,T54,T22	Yes	T2,T48,T49	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T48,T49	Yes	T2,T48,T49	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T9,T50	Yes	T1,T9,T50	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T56,T57,T12	Yes	T9,T50,T56	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T9,T50	Yes	T1,T9,T50	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T51,T52,T11	Yes	T51,T52,T11	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T11,T58,T50	Yes	T11,T58,T50	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T51,T52,T11	Yes	T51,T52,T11	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T25	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T25,T26	Yes	T2,T25,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T25,T26	Yes	T25,T26,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T33,T59,T6	Yes	T33,T59,T6	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T27,T32	Yes	T10,T27,T32	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T27,T5,T6	Yes	T27,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T27,T32	Yes	T10,T27,T32	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T27,T5,T6	Yes	T27,T5,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T43,T44	Yes	T4,T43,T44	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T43,T44	Yes	T4,T43,T44	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	186287800	186091570	0	0
CsrngAppIfOut_A	186287800	186091570	0	0
FpvSecCmCntAlertCheck_A	186287800	137	0	0
FpvSecCmGenCmdFifoRptrCheck_A	186287800	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	186287800	90	0	0
FpvSecCmMainFsmCheck_A	186287800	90	0	0
FpvSecCmRegWeOnehotCheck_A	186287800	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	186287800	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	186287800	90	0	0
IntrEdnCmdReqDoneKnownO_A	186287800	186091570	0	0
TlAReadyKnownO_A	186287800	186091570	0	0
TlDValidKnownO_A	186287800	186091570	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	186287800	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[0].EdnDataStable_A	186287800	24673	0	432
gen_edn_if_asserts[0].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[1].EdnDataStable_A	186287800	3287	0	118
gen_edn_if_asserts[1].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[2].EdnDataStable_A	186287800	6295	0	108
gen_edn_if_asserts[2].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[3].EdnDataStable_A	186287800	4021	0	115
gen_edn_if_asserts[3].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[4].EdnDataStable_A	186287800	4493	0	87
gen_edn_if_asserts[4].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[5].EdnDataStable_A	186287800	3760	0	98
gen_edn_if_asserts[5].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	186287800	168501	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	186287800	579154	0	320
gen_edn_if_asserts[6].EdnDataStable_A	186287800	1864	0	73
gen_edn_if_asserts[6].EdnEndPointOut_A	186287800	186091570	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	186287800	168501	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	137	0	0
T7	783	0	0	0
T14	526	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	20	0	0
T34	2092	0	0	0
T58	647	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	2017	0	0	0
T67	2045	0	0	0
T68	1619	0	0	0
T69	2085	0	0	0
T70	516	0	0	0
T71	1854	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	90	0	0
T17	58414	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T62	1162	0	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	1037	0	0	0
T75	2235	0	0	0
T76	2365	0	0	0
T77	2923	0	0	0
T78	2399	0	0	0
T79	7841	0	0	0
T80	2179	0	0	0
T81	2875	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	24673	0	432
T3	1212	3	0	1
T4	331516	64	0	0
T9	3586	0	0	0
T10	2750	4	0	1
T23	3744	4	0	0
T25	1390	27	0	1
T26	2994	12	0	1
T27	3912	0	0	0
T28	4075	0	0	0
T33	0	4	0	1
T45	0	62	0	1
T47	1384	0	0	0
T48	0	0	0	1
T59	0	4	0	1
T85	0	28	0	1
T86	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	3287	0	118
T8	0	1	0	0
T21	0	47	0	1
T23	3744	0	0	0
T28	4075	62	0	1
T32	2330	0	0	0
T33	2150	0	0	0
T45	4077	3	0	1
T46	3321	3	0	1
T47	1384	0	0	0
T48	0	27	0	1
T50	0	0	0	1
T51	1067	0	0	0
T55	0	3	0	1
T59	1986	0	0	0
T85	2209	0	0	0
T92	0	3	0	1
T93	0	4	0	1
T94	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	6295	0	108
T5	831	0	0	0
T21	0	459	0	1
T22	0	3	0	1
T32	2330	4	0	1
T33	2150	0	0	0
T45	4077	19	0	1
T46	3321	32	0	1
T47	1384	3	0	1
T48	4744	0	0	0
T50	0	3	0	1
T51	1067	0	0	0
T59	1986	0	0	0
T85	2209	0	0	0
T95	0	3	0	1
T96	0	4	0	1
T97	0	4	0	0
T98	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	4021	0	115
T5	831	1	0	0
T6	1876	0	0	0
T22	0	3	0	1
T32	2330	0	0	0
T33	2150	0	0	0
T35	0	1	0	0
T45	4077	26	0	1
T46	3321	0	0	0
T48	4744	0	0	0
T51	1067	0	0	0
T53	0	3	0	1
T54	0	16	0	1
T55	0	59	0	1
T56	0	48	0	1
T57	0	0	0	1
T59	1986	0	0	0
T85	2209	0	0	0
T99	0	4	0	1
T100	0	17	0	1
T101	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	4493	0	87
T2	2958	4	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T9	3586	0	0	0
T10	2750	0	0	0
T11	0	10	0	1
T22	0	50	0	1
T23	3744	0	0	0
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T48	0	3	0	1
T49	0	15	0	1
T54	0	29	0	1
T57	0	3	0	1
T99	0	4	0	0
T102	0	4	0	0
T103	0	4	0	0
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	3760	0	98
T1	1337	4	0	0
T2	2958	0	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T9	3586	4	0	0
T10	2750	0	0	0
T12	0	15	0	1
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T50	0	3	0	1
T56	0	46	0	1
T57	0	49	0	1
T104	0	53	0	1
T105	0	0	0	1
T108	0	3	0	1
T109	0	31	0	1
T110	0	4	0	1
T111	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	579154	0	320
T1	1337	79	0	0
T2	2958	1349	0	2
T3	1212	121	0	0
T4	331516	850	0	2
T9	3586	2019	0	2
T10	2750	388	0	0
T23	0	0	0	2
T25	1390	18	0	0
T26	2994	36	0	0
T27	3912	3812	0	2
T28	4075	16	0	0
T43	0	0	0	2
T44	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	1864	0	73
T5	831	0	0	0
T6	1876	0	0	0
T11	0	35	0	1
T22	0	3	0	1
T32	2330	0	0	0
T33	2150	0	0	0
T39	683	0	0	0
T46	3321	0	0	0
T48	4744	0	0	0
T50	0	22	0	1
T51	1067	3	0	1
T52	0	4	0	0
T57	0	3	0	1
T58	0	4	0	0
T59	1986	0	0	0
T85	2209	0	0	0
T104	0	3	0	1
T105	0	3	0	1
T107	0	0	0	1
T112	0	4	0	0
T113	0	0	0	1
T114	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	168501	0	0
T5	831	362	0	0
T6	1876	1072	0	0
T7	0	332	0	0
T14	0	205	0	0
T34	0	37	0	0
T35	0	7	0	0
T39	683	352	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	252	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1112	0	0
T88	0	1146	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0