Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	186807069	8406689	0	0
boot_gen_cmd_rd_A	186807069	30556	0	0
boot_ins_cmd_rd_A	186807069	35938	0	0
ctrl_rd_A	186807069	31378	0	0
err_code_test_rd_A	186807069	36210	0	0
intr_enable_rd_A	186807069	36424	0	0
max_num_reqs_between_reseeds_rd_A	186807069	33075	0	0
regwen_rd_A	186807069	35907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	8406689	0	0
T4	331516	187033	0	0
T23	3744	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T32	2330	0	0	0
T43	0	212840	0	0
T44	0	80005	0	0
T45	4077	0	0	0
T46	3321	0	0	0
T47	1384	0	0	0
T51	1067	0	0	0
T84	0	69154	0	0
T85	2209	0	0	0
T120	0	245786	0	0
T239	0	98169	0	0
T240	0	117327	0	0
T241	0	235843	0	0
T242	0	220261	0	0
T243	0	193101	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	30556	0	0
T42	596	0	0	0
T105	2461	0	0	0
T106	1937	0	0	0
T111	816	0	0	0
T138	1799	0	0	0
T240	318577	3422	0	0
T244	0	5618	0	0
T245	0	766	0	0
T246	0	2155	0	0
T247	0	1811	0	0
T248	0	4218	0	0
T249	0	1948	0	0
T250	0	2265	0	0
T251	0	1763	0	0
T252	0	2455	0	0
T253	2592	0	0	0
T254	3030	0	0	0
T255	1387	0	0	0
T256	2233	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	35938	0	0
T42	596	0	0	0
T105	2461	0	0	0
T106	1937	0	0	0
T111	816	0	0	0
T138	1799	0	0	0
T240	318577	3776	0	0
T244	0	6362	0	0
T245	0	765	0	0
T246	0	2545	0	0
T247	0	2268	0	0
T248	0	5052	0	0
T249	0	2684	0	0
T250	0	2610	0	0
T251	0	2175	0	0
T252	0	2944	0	0
T253	2592	0	0	0
T254	3030	0	0	0
T255	1387	0	0	0
T256	2233	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	31378	0	0
T8	2808	3	0	0
T15	572	0	0	0
T22	6396	0	0	0
T50	3560	0	0	0
T99	2411	0	0	0
T119	9448	0	0	0
T120	599594	0	0	0
T122	2053	0	0	0
T125	2509	0	0	0
T240	0	3113	0	0
T244	0	5875	0	0
T245	0	805	0	0
T246	0	2180	0	0
T247	0	1884	0	0
T257	0	5	0	0
T258	0	2	0	0
T259	0	8	0	0
T260	0	5	0	0
T261	1101	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	36210	0	0
T42	596	0	0	0
T105	2461	0	0	0
T106	1937	0	0	0
T111	816	0	0	0
T138	1799	0	0	0
T240	318577	3954	0	0
T244	0	6628	0	0
T245	0	835	0	0
T246	0	2500	0	0
T247	0	2143	0	0
T248	0	5322	0	0
T249	0	2622	0	0
T250	0	2674	0	0
T251	0	2183	0	0
T252	0	2810	0	0
T253	2592	0	0	0
T254	3030	0	0	0
T255	1387	0	0	0
T256	2233	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	36424	0	0
T30	852	0	0	0
T36	1239	0	0	0
T56	4630	0	0	0
T98	2762	0	0	0
T102	2194	0	0	0
T179	2062	0	0	0
T213	3539	0	0	0
T240	0	3829	0	0
T244	0	5790	0	0
T245	0	978	0	0
T246	0	2159	0	0
T247	0	2149	0	0
T262	8217	11	0	0
T263	0	7	0	0
T264	0	81	0	0
T265	0	77	0	0
T266	0	24	0	0
T267	1571	0	0	0
T268	5499	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	33075	0	0
T42	596	0	0	0
T105	2461	0	0	0
T106	1937	0	0	0
T111	816	0	0	0
T138	1799	0	0	0
T240	318577	3599	0	0
T244	0	5862	0	0
T245	0	780	0	0
T246	0	1924	0	0
T247	0	1857	0	0
T248	0	4701	0	0
T249	0	2377	0	0
T250	0	2261	0	0
T251	0	1539	0	0
T252	0	2776	0	0
T253	2592	0	0	0
T254	3030	0	0	0
T255	1387	0	0	0
T256	2233	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186807069	35907	0	0
T42	596	0	0	0
T105	2461	0	0	0
T106	1937	0	0	0
T111	816	0	0	0
T138	1799	0	0	0
T240	318577	3504	0	0
T244	0	6297	0	0
T245	0	897	0	0
T246	0	2146	0	0
T247	0	2097	0	0
T248	0	4852	0	0
T249	0	2700	0	0
T250	0	2759	0	0
T251	0	1936	0	0
T252	0	2822	0	0
T253	2592	0	0	0
T254	3030	0	0	0
T255	1387	0	0	0
T256	2233	0	0	0