Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39	98.25	93.91	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.31	99.92	92.66	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T8,T9

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T20,T21
1	0	Covered	T4,T5,T34

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T8,T26	Yes	T1,T8,T26	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T16,T43	Yes	T4,T16,T43	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T8,T34	Yes	T3,T8,T34	INPUT
edn_i[3].edn_req	Yes	Yes	T44,T45,T14	Yes	T44,T45,T14	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T5,T43	Yes	T3,T5,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T37,T43,T15	Yes	T37,T43,T15	INPUT
edn_i[6].edn_req	Yes	Yes	T43,T46,T47	Yes	T43,T46,T47	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T25	Yes	T1,T2,T25	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T25,T27	Yes	T1,T25,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T43,T22,T48	Yes	T43,T15,T22	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T43,T22,T48	Yes	T43,T15,T22	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T43,T15,T22	Yes	T43,T15,T22	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T8,T34	Yes	T3,T8,T34	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T15,T22,T49	Yes	T3,T43,T15	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T8,T34	Yes	T3,T8,T34	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T44,T45,T14	Yes	T44,T45,T14	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T50,T10,T51	Yes	T44,T15,T50	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T44,T45,T14	Yes	T44,T45,T14	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T15,T22	Yes	T3,T43,T15	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T15,T52	Yes	T3,T15,T22	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T43,T15	Yes	T3,T43,T15	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T43,T15,T46	Yes	T43,T15,T46	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T50,T52,T53	Yes	T43,T50,T52	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T37,T43,T15	Yes	T37,T43,T15	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T43,T46,T47	Yes	T43,T46,T47	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T46,T22	Yes	T43,T46,T22	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T43,T46,T47	Yes	T43,T46,T47	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T25	Yes	T1,T3,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T25	Yes	T1,T3,T25	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T45,T49,T54	Yes	T45,T49,T54	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T55	Yes	T4,T5,T55	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T55	Yes	T4,T5,T55	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T56,T57	Yes	T1,T56,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T56,T57	Yes	T1,T56,T57	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	221344259	221163048	0	0
CsrngAppIfOut_A	221344259	221163048	0	0
FpvSecCmCntAlertCheck_A	221344259	105	0	0
FpvSecCmGenCmdFifoRptrCheck_A	221344259	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	221344259	70	0	0
FpvSecCmMainFsmCheck_A	221344259	70	0	0
FpvSecCmRegWeOnehotCheck_A	221344259	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	221344259	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	221344259	70	0	0
IntrEdnCmdReqDoneKnownO_A	221344259	221163048	0	0
TlAReadyKnownO_A	221344259	221163048	0	0
TlDValidKnownO_A	221344259	221163048	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	221344259	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[0].EdnDataStable_A	221344259	29204	0	418
gen_edn_if_asserts[0].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[1].EdnDataStable_A	221344259	4838	0	136
gen_edn_if_asserts[1].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[2].EdnDataStable_A	221344259	4168	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[3].EdnDataStable_A	221344259	6418	0	102
gen_edn_if_asserts[3].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[4].EdnDataStable_A	221344259	2640	0	82
gen_edn_if_asserts[4].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[5].EdnDataStable_A	221344259	3111	0	70
gen_edn_if_asserts[5].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	221344259	142653	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	221344259	616846	0	318
gen_edn_if_asserts[6].EdnDataStable_A	221344259	1277	0	74
gen_edn_if_asserts[6].EdnEndPointOut_A	221344259	221163048	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	221344259	142653	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	105	0	0
T14	2069	0	0	0
T15	2616	0	0	0
T16	1840	1	0	0
T17	1044	1	0	0
T18	0	1	0	0
T43	4144	0	0	0
T46	1872	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	1253	0	0	0
T66	15440	0	0	0
T67	4472	0	0	0
T68	1877	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	70	0	0
T19	30894	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T69	0	10	0	0
T70	0	10	0	0
T71	2156	0	0	0
T72	2779	0	0	0
T73	2415	0	0	0
T74	804	0	0	0
T75	1906	0	0	0
T76	1727	0	0	0
T77	1781	0	0	0
T78	3828	0	0	0
T79	1437	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	29204	0	418
T1	22644	22	0	0
T2	1827	4	0	1
T3	1954	3	0	1
T4	2376	0	0	0
T5	1857	0	0	0
T8	2901	0	0	0
T9	2359	4	0	1
T25	1673	36	0	1
T26	1046	3	0	1
T27	3381	71	0	1
T40	0	80	0	0
T56	0	26	0	1
T57	0	14	0	1
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	4838	0	136
T10	0	15	0	1
T15	2616	3	0	1
T17	1044	0	0	0
T22	0	535	0	1
T43	4144	54	0	1
T46	1872	0	0	0
T47	879	0	0	0
T48	0	33	0	1
T51	0	17	0	1
T52	0	3	0	1
T65	1253	0	0	0
T66	15440	0	0	0
T67	4472	0	0	0
T68	1877	0	0	0
T81	992	0	0	0
T89	0	3	0	1
T90	0	31	0	1
T91	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	4168	0	127
T3	1954	4	0	1
T4	2376	0	0	0
T5	1857	0	0	0
T8	2901	4	0	1
T9	2359	0	0	0
T10	0	0	0	1
T15	0	32	0	1
T22	0	40	0	1
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T34	0	1	0	0
T43	0	19	0	1
T49	0	4	0	0
T52	0	3	0	1
T56	25626	0	0	0
T57	13182	0	0	0
T89	0	27	0	1
T92	0	3	0	1
T93	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	6418	0	102
T10	0	22	0	1
T14	2069	4	0	0
T15	0	3	0	1
T16	1840	0	0	0
T17	1044	0	0	0
T43	4144	3	0	1
T44	1216	11	0	1
T45	1977	4	0	1
T50	0	44	0	1
T51	0	0	0	1
T52	0	3	0	1
T53	0	3	0	1
T65	1253	0	0	0
T66	15440	0	0	0
T67	4472	0	0	0
T68	1877	0	0	0
T94	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	2640	0	82
T3	1954	55	0	1
T4	2376	0	0	0
T5	1857	0	0	0
T8	2901	0	0	0
T9	2359	0	0	0
T10	0	3	0	1
T11	0	0	0	1
T15	0	21	0	1
T22	0	5	0	1
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T43	0	3	0	1
T49	0	4	0	1
T50	0	3	0	1
T52	0	37	0	1
T56	25626	0	0	0
T57	13182	0	0	0
T83	0	4	0	0
T95	0	4	0	0
T96	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	3111	0	70
T10	0	0	0	1
T11	0	0	0	1
T13	3252	0	0	0
T14	2069	0	0	0
T15	0	7	0	1
T16	1840	0	0	0
T17	1044	0	0	0
T37	849	1	0	0
T43	4144	3	0	1
T44	1216	0	0	0
T45	1977	0	0	0
T46	0	4	0	1
T50	0	21	0	1
T51	0	0	0	1
T52	0	40	0	1
T53	0	59	0	1
T65	1253	0	0	0
T80	1143	0	0	0
T83	0	1	0	0
T97	0	4	0	0
T98	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	616846	0	318
T1	22644	3158	0	0
T2	1827	187	0	0
T3	1954	15	0	0
T4	2376	1608	0	0
T5	1857	1065	0	0
T8	2901	203	0	0
T9	2359	250	0	0
T14	0	0	0	2
T23	0	0	0	2
T25	1673	16	0	0
T26	1046	12	0	0
T27	3381	53	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T55	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	1277	0	74
T10	0	3	0	1
T11	0	3	0	1
T15	2616	0	0	0
T17	1044	0	0	0
T22	0	58	0	1
T23	0	4	0	0
T43	4144	8	0	1
T46	1872	4	0	0
T47	879	3	0	1
T51	0	3	0	1
T52	0	42	0	1
T53	0	37	0	1
T65	1253	0	0	0
T66	15440	0	0	0
T67	4472	0	0	0
T68	1877	0	0	0
T81	992	0	0	0
T90	0	0	0	1
T99	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	142653	0	0
T4	2376	1117	0	0
T5	1857	1146	0	0
T6	0	1176	0	0
T16	0	415	0	0
T17	0	604	0	0
T34	731	21	0	0
T37	849	350	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	612	0	0
T87	0	1100	0	0
T88	0	1150	0	0