Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221849108	9307322	0	0
boot_gen_cmd_rd_A	221849108	91532	0	0
boot_ins_cmd_rd_A	221849108	105703	0	0
ctrl_rd_A	221849108	92436	0	0
err_code_test_rd_A	221849108	105849	0	0
intr_enable_rd_A	221849108	101724	0	0
max_num_reqs_between_reseeds_rd_A	221849108	92798	0	0
regwen_rd_A	221849108	105892	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	9307322	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	134662	0	0
T41	0	108498	0	0
T42	0	195832	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	121697	0	0
T227	0	89369	0	0
T228	0	239029	0	0
T229	0	333269	0	0
T230	0	84782	0	0
T231	0	589005	0	0
T232	0	90166	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	91532	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	3853	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	3416	0	0
T227	0	2494	0	0
T232	0	2480	0	0
T233	0	6142	0	0
T234	0	4010	0	0
T235	0	2297	0	0
T236	0	2623	0	0
T237	0	2710	0	0
T238	0	6179	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	105703	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	4540	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	4132	0	0
T227	0	2987	0	0
T232	0	2987	0	0
T233	0	7168	0	0
T234	0	4725	0	0
T235	0	2636	0	0
T236	0	2784	0	0
T237	0	3302	0	0
T238	0	6710	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	92436	0	0
T13	3252	0	0	0
T29	0	2	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	3959	0	0
T55	1460	0	0	0
T56	25626	1	0	0
T57	13182	0	0	0
T66	0	3	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	3775	0	0
T109	0	3	0	0
T159	0	1	0	0
T227	0	2496	0	0
T232	0	2611	0	0
T239	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	105849	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	4526	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	4358	0	0
T227	0	2968	0	0
T232	0	3058	0	0
T233	0	7172	0	0
T234	0	4592	0	0
T235	0	2588	0	0
T236	0	2950	0	0
T237	0	3721	0	0
T238	0	6969	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	101724	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	4498	0	0
T55	1460	0	0	0
T56	25626	41	0	0
T57	13182	0	0	0
T66	0	29	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	3696	0	0
T109	0	75	0	0
T110	0	14	0	0
T227	0	2634	0	0
T232	0	2672	0	0
T240	0	58	0	0
T241	0	51	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	92798	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	4224	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	3673	0	0
T227	0	2648	0	0
T232	0	2469	0	0
T233	0	6080	0	0
T234	0	4032	0	0
T235	0	2164	0	0
T236	0	2549	0	0
T237	0	3035	0	0
T238	0	6058	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221849108	105892	0	0
T13	3252	0	0	0
T34	731	0	0	0
T37	849	0	0	0
T40	387377	4474	0	0
T44	1216	0	0	0
T45	1977	0	0	0
T55	1460	0	0	0
T80	1143	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T108	0	4137	0	0
T227	0	2958	0	0
T232	0	2797	0	0
T233	0	6951	0	0
T234	0	4783	0	0
T235	0	2615	0	0
T236	0	2825	0	0
T237	0	3475	0	0
T238	0	6723	0	0