Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.19	98.25	93.85	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.10	99.92	92.58	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T9,T41

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T20
1	0	Covered	T43,T28,T15

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T24,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T23,T9	Yes	T1,T23,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T48,T49	Yes	T5,T48,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T23,T9	Yes	T1,T23,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T3,T23	Yes	T2,T3,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T18,T31	Yes	T27,T18,T31	INPUT
edn_i[3].edn_req	Yes	Yes	T18,T10,T50	Yes	T18,T10,T50	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T27,T51	Yes	T2,T27,T51	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T24,T27	Yes	T2,T24,T27	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T23,T9	Yes	T1,T23,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T27,T5,T41	Yes	T1,T9,T25	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T23,T9	Yes	T1,T23,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T3,T23	Yes	T2,T3,T23	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T52,T53	Yes	T2,T3,T23	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T3,T23	Yes	T2,T3,T23	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T18,T31,T21	Yes	T27,T18,T31	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T21,T51,T54	Yes	T31,T21,T51	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T18,T31	Yes	T27,T18,T31	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T18,T10,T50	Yes	T18,T10,T50	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T21,T54,T55	Yes	T10,T50,T21	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T18,T10,T50	Yes	T18,T10,T50	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T2,T28,T56	Yes	T2,T27,T28	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T27,T51	Yes	T2,T27,T51	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T27,T57	Yes	T2,T27,T51	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T27,T51	Yes	T2,T27,T51	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T24,T27	Yes	T2,T24,T27	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T2,T27,T56	Yes	T2,T27,T58	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T24,T27	Yes	T2,T24,T27	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T23	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T23,T9	Yes	T2,T27,T5	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T27,T5	Yes	T2,T23,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T18,T10	Yes	T9,T18,T10	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T9,T41	Yes	T3,T9,T41	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T43,T28,T15	Yes	T43,T28,T15	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T9,T41	Yes	T3,T9,T41	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T43,T28,T15	Yes	T43,T28,T15	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T38	Yes	T4,T5,T38	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T38	Yes	T4,T5,T38	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	209144438	208956017	0	0
CsrngAppIfOut_A	209144438	208956017	0	0
FpvSecCmCntAlertCheck_A	209144438	120	0	0
FpvSecCmGenCmdFifoRptrCheck_A	209144438	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	209144438	80	0	0
FpvSecCmMainFsmCheck_A	209144438	80	0	0
FpvSecCmRegWeOnehotCheck_A	209144438	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	209144438	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	209144438	80	0	0
IntrEdnCmdReqDoneKnownO_A	209144438	208956017	0	0
TlAReadyKnownO_A	209144438	208956017	0	0
TlDValidKnownO_A	209144438	208956017	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	209144438	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[0].EdnDataStable_A	209144438	69360	0	398
gen_edn_if_asserts[0].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[1].EdnDataStable_A	209144438	5903	0	143
gen_edn_if_asserts[1].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[2].EdnDataStable_A	209144438	5808	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[3].EdnDataStable_A	209144438	5314	0	116
gen_edn_if_asserts[3].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[4].EdnDataStable_A	209144438	5140	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[5].EdnDataStable_A	209144438	2498	0	94
gen_edn_if_asserts[5].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	209144438	147027	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	209144438	542516	0	316
gen_edn_if_asserts[6].EdnDataStable_A	209144438	2230	0	77
gen_edn_if_asserts[6].EdnEndPointOut_A	209144438	208956017	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	209144438	147027	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	120	0	0
T15	1114	1	0	0
T16	0	10	0	0
T17	0	1	0	0
T19	0	20	0	0
T20	0	10	0	0
T32	2166	0	0	0
T44	1876	0	0	0
T55	2175	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1666	0	0	0
T65	860	0	0	0
T66	12360	0	0	0
T67	2125	0	0	0
T68	807	0	0	0
T69	3047	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	80	0	0
T16	23550	10	0	0
T17	675	0	0	0
T19	0	20	0	0
T20	0	10	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	1708	0	0	0
T73	432	0	0	0
T74	3064	0	0	0
T75	1177	0	0	0
T76	5651	0	0	0
T77	2831	0	0	0
T78	2160	0	0	0
T79	119675	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	69360	0	398
T1	1897	3	0	1
T2	2709	0	0	0
T3	1995	0	0	0
T4	6202	10	0	1
T5	0	118	0	1
T9	2442	4	0	1
T23	4275	3	0	1
T24	1389	0	0	0
T25	1162	3	0	1
T26	1093	0	0	0
T27	2271	42	0	1
T33	0	3	0	1
T41	0	8	0	1
T86	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	5903	0	143
T2	2709	50	0	1
T3	1995	4	0	1
T4	6202	0	0	0
T9	2442	0	0	0
T21	0	3	0	1
T23	4275	9	0	1
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	3	0	1
T27	2271	3	0	1
T33	1254	0	0	0
T50	0	3	0	1
T54	0	3	0	1
T67	0	0	0	1
T93	0	4	0	1
T94	0	4	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	5808	0	129
T5	402946	0	0	0
T10	2314	0	0	0
T18	2630	4	0	1
T21	0	21	0	1
T27	2271	3	0	1
T31	0	4	0	1
T33	1254	0	0	0
T38	21055	0	0	0
T41	2658	0	0	0
T43	0	1	0	0
T50	0	3	0	1
T51	0	63	0	1
T54	0	10	0	1
T58	2403	0	0	0
T86	1174	0	0	0
T95	0	3	0	1
T96	0	3	0	1
T97	2004	0	0	0
T98	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	5314	0	116
T10	2314	4	0	1
T11	3855	0	0	0
T18	2630	4	0	0
T21	0	1011	0	1
T31	1929	0	0	0
T38	21055	0	0	0
T43	2281	0	0	0
T50	0	11	0	1
T54	0	17	0	1
T55	0	47	0	1
T57	0	52	0	1
T77	0	0	0	1
T93	2206	0	0	0
T94	2198	0	0	0
T97	2004	0	0	0
T99	0	3	0	1
T100	0	31	0	1
T101	0	4	0	1
T102	1743	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	5140	0	104
T2	2709	61	0	1
T3	1995	0	0	0
T4	6202	0	0	0
T9	2442	0	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	3	0	1
T28	0	1	0	0
T33	1254	0	0	0
T34	0	4	0	1
T54	0	3	0	1
T55	0	30	0	1
T56	0	26	0	1
T57	0	0	0	1
T95	0	0	0	1
T103	0	4	0	0
T104	0	4	0	1
T105	0	8	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	2498	0	94
T2	2709	57	0	1
T3	1995	0	0	0
T4	6202	0	0	0
T9	2442	0	0	0
T22	0	1	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	33	0	1
T32	0	4	0	1
T33	1254	0	0	0
T51	0	13	0	1
T54	0	3	0	1
T57	0	19	0	1
T95	0	3	0	1
T98	0	0	0	1
T103	0	4	0	1
T106	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	542516	0	316
T1	1897	97	0	0
T2	2709	59	0	0
T3	1995	296	0	0
T4	6202	658	0	0
T9	2442	139	0	0
T22	0	0	0	2
T23	4275	21	0	0
T24	1389	190	0	0
T25	1162	13	0	0
T26	1093	45	0	0
T27	2271	14	0	0
T38	0	0	0	2
T48	0	0	0	2
T65	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2
T85	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	2230	0	77
T2	2709	39	0	1
T3	1995	0	0	0
T4	6202	0	0	0
T9	2442	0	0	0
T23	4275	0	0	0
T24	1389	3	0	1
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	36	0	1
T33	1254	0	0	0
T54	0	3	0	1
T55	0	13	0	1
T56	0	42	0	1
T57	0	29	0	1
T58	0	3	0	1
T68	0	1	0	0
T98	0	26	0	1
T100	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	147027	0	0
T6	0	401	0	0
T15	0	643	0	0
T21	7929	0	0	0
T28	1255	7	0	0
T42	0	16	0	0
T43	2281	1147	0	0
T44	0	1123	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	360	0	0
T87	0	744	0	0
T88	0	258	0	0
T89	0	1140	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0