Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	209594292	9508572	0	0
boot_gen_cmd_rd_A	209594292	68214	0	0
boot_ins_cmd_rd_A	209594292	78115	0	0
ctrl_rd_A	209594292	69101	0	0
err_code_test_rd_A	209594292	79105	0	0
intr_enable_rd_A	209594292	75250	0	0
max_num_reqs_between_reseeds_rd_A	209594292	69940	0	0
regwen_rd_A	209594292	78602	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	9508572	0	0
T5	402946	239145	0	0
T10	2314	0	0	0
T11	3855	0	0	0
T18	2630	0	0	0
T38	21055	0	0	0
T41	2658	0	0	0
T48	0	87780	0	0
T49	0	255023	0	0
T58	2403	0	0	0
T79	0	41708	0	0
T83	0	249097	0	0
T84	0	106051	0	0
T86	1174	0	0	0
T93	2206	0	0	0
T97	2004	0	0	0
T238	0	152788	0	0
T239	0	98158	0	0
T240	0	282934	0	0
T241	0	189383	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	68214	0	0
T49	754192	7128	0	0
T79	0	1205	0	0
T83	719778	7366	0	0
T84	0	2938	0	0
T95	2949	0	0	0
T96	2362	0	0	0
T99	991	0	0	0
T182	844	0	0	0
T208	1324	0	0	0
T229	1065	0	0	0
T242	0	3557	0	0
T243	0	4655	0	0
T244	0	8315	0	0
T245	0	1581	0	0
T246	0	2239	0	0
T247	0	361	0	0
T248	937	0	0	0
T249	1254	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	78115	0	0
T49	754192	8651	0	0
T79	0	1318	0	0
T83	719778	8315	0	0
T84	0	3160	0	0
T95	2949	0	0	0
T96	2362	0	0	0
T99	991	0	0	0
T182	844	0	0	0
T208	1324	0	0	0
T229	1065	0	0	0
T242	0	4253	0	0
T243	0	5608	0	0
T244	0	9533	0	0
T245	0	1704	0	0
T246	0	2704	0	0
T247	0	455	0	0
T248	937	0	0	0
T249	1254	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	69101	0	0
T11	3855	5	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T31	1929	0	0	0
T43	2281	0	0	0
T49	0	7483	0	0
T50	2242	0	0	0
T79	0	1170	0	0
T83	0	7282	0	0
T84	0	2952	0	0
T90	1895	0	0	0
T93	2206	0	0	0
T94	2198	0	0	0
T102	1743	0	0	0
T242	0	3496	0	0
T243	0	4727	0	0
T244	0	8325	0	0
T245	0	1604	0	0
T250	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	79105	0	0
T49	754192	8776	0	0
T79	0	1246	0	0
T83	719778	8464	0	0
T84	0	3423	0	0
T95	2949	0	0	0
T96	2362	0	0	0
T99	991	0	0	0
T182	844	0	0	0
T208	1324	0	0	0
T229	1065	0	0	0
T242	0	4217	0	0
T243	0	5119	0	0
T244	0	9730	0	0
T245	0	1730	0	0
T246	0	2379	0	0
T247	0	508	0	0
T248	937	0	0	0
T249	1254	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	75250	0	0
T4	6202	29	0	0
T5	402946	0	0	0
T18	2630	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	0	0	0
T33	1254	0	0	0
T38	0	28	0	0
T41	2658	0	0	0
T49	0	7411	0	0
T58	2403	0	0	0
T79	0	1340	0	0
T81	0	26	0	0
T83	0	7482	0	0
T84	0	3407	0	0
T86	1174	0	0	0
T242	0	3964	0	0
T243	0	5562	0	0
T244	0	8648	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	69940	0	0
T49	754192	7072	0	0
T79	0	1119	0	0
T83	719778	7768	0	0
T84	0	3151	0	0
T95	2949	0	0	0
T96	2362	0	0	0
T99	991	0	0	0
T182	844	0	0	0
T208	1324	0	0	0
T229	1065	0	0	0
T242	0	3682	0	0
T243	0	4838	0	0
T244	0	8551	0	0
T245	0	1397	0	0
T246	0	2122	0	0
T247	0	381	0	0
T248	937	0	0	0
T249	1254	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209594292	78602	0	0
T49	754192	8354	0	0
T79	0	1502	0	0
T83	719778	8418	0	0
T84	0	3354	0	0
T95	2949	0	0	0
T96	2362	0	0	0
T99	991	0	0	0
T182	844	0	0	0
T208	1324	0	0	0
T229	1065	0	0	0
T242	0	3978	0	0
T243	0	5250	0	0
T244	0	9988	0	0
T245	0	1536	0	0
T246	0	2517	0	0
T247	0	376	0	0
T248	937	0	0	0
T249	1254	0	0	0