Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T21,T10,T20

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T4,T5,T32

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T21,T10	Yes	T1,T21,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T21,T10	Yes	T1,T21,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T35,T36	Yes	T1,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T21,T10	Yes	T1,T3,T21	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T22,T23,T15	Yes	T22,T23,T15	INPUT
edn_i[2].edn_req	Yes	Yes	T15,T12,T37	Yes	T15,T12,T37	INPUT
edn_i[3].edn_req	Yes	Yes	T9,T15,T12	Yes	T9,T15,T12	INPUT
edn_i[4].edn_req	Yes	Yes	T9,T15,T38	Yes	T9,T15,T38	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T21,T9	Yes	T3,T21,T9	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T4,T15	Yes	T9,T4,T15	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T22,T15	Yes	T1,T22,T24	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T15,T12	Yes	T22,T23,T15	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T23,T12,T13	Yes	T23,T15,T12	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T22,T23,T15	Yes	T22,T23,T15	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T15,T12,T37	Yes	T15,T12,T37	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T15,T12,T37	Yes	T15,T12,T37	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T15,T12,T37	Yes	T15,T12,T37	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T9,T15,T12	Yes	T9,T15,T12	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T15,T13,T39	Yes	T9,T15,T12	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T9,T15,T12	Yes	T9,T15,T12	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T9,T15,T12	Yes	T9,T15,T38	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T37,T13	Yes	T9,T15,T12	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T9,T15,T38	Yes	T9,T15,T38	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T21,T9	Yes	T3,T21,T9	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T15,T40,T37	Yes	T3,T15,T40	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T21,T9	Yes	T3,T21,T9	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T15,T12	Yes	T9,T15,T12	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T9,T15,T40	Yes	T9,T15,T12	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T15,T12	Yes	T9,T15,T12	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T21	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T9	Yes	T1,T9,T22	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T9,T22	Yes	T1,T3,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T21,T5,T41	Yes	T21,T5,T41	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T10,T20	Yes	T21,T10,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T32	Yes	T4,T5,T32	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T10,T20	Yes	T21,T10,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T32	Yes	T4,T5,T32	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T42,T35	Yes	T1,T42,T35	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T32,T42	Yes	T1,T32,T42	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	249757816	249596535	0	0
CsrngAppIfOut_A	249757816	249596535	0	0
FpvSecCmCntAlertCheck_A	249757816	97	0	0
FpvSecCmGenCmdFifoRptrCheck_A	249757816	50	0	0
FpvSecCmGenCmdFifoWptrCheck_A	249757816	50	0	0
FpvSecCmMainFsmCheck_A	249757816	50	0	0
FpvSecCmRegWeOnehotCheck_A	249757816	50	0	0
FpvSecCmResCmdFifoRptrCheck_A	249757816	50	0	0
FpvSecCmResCmdFifoWptrCheck_A	249757816	50	0	0
IntrEdnCmdReqDoneKnownO_A	249757816	249596535	0	0
TlAReadyKnownO_A	249757816	249596535	0	0
TlDValidKnownO_A	249757816	249596535	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	249757816	50	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[0].EdnDataStable_A	249757816	17112	0	409
gen_edn_if_asserts[0].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[1].EdnDataStable_A	249757816	5327	0	122
gen_edn_if_asserts[1].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[2].EdnDataStable_A	249757816	4819	0	114
gen_edn_if_asserts[2].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[3].EdnDataStable_A	249757816	6683	0	100
gen_edn_if_asserts[3].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[4].EdnDataStable_A	249757816	54065	0	108
gen_edn_if_asserts[4].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[5].EdnDataStable_A	249757816	1943	0	87
gen_edn_if_asserts[5].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	249757816	128868	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	249757816	561111	0	320
gen_edn_if_asserts[6].EdnDataStable_A	249757816	2925	0	90
gen_edn_if_asserts[6].EdnEndPointOut_A	249757816	249596535	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	249757816	128868	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	97	0	0
T4	1892	1	0	0
T5	1472	0	0	0
T8	0	1	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	10	0	0
T17	0	1	0	0
T20	1768	0	0	0
T38	813	0	0	0
T40	2191	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	2099	0	0	0
T50	2788	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	50	0	0
T13	3173	0	0	0
T16	21740	10	0	0
T18	0	10	0	0
T19	0	10	0	0
T30	764	0	0	0
T35	836642	0	0	0
T51	0	10	0	0
T52	0	10	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T58	3179	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	17112	0	409
T1	504975	39	0	0
T2	1464	3	0	1
T3	1519	0	0	0
T4	1892	0	0	0
T9	4739	0	0	0
T10	2482	4	0	1
T11	0	4	0	0
T12	0	3	0	1
T15	0	54	0	1
T20	0	4	0	1
T21	1893	0	0	0
T22	4103	49	0	1
T23	1004	0	0	0
T24	2888	3	0	1
T40	0	60	0	1
T49	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	5327	0	122
T4	1892	0	0	0
T10	2482	0	0	0
T11	1867	0	0	0
T12	2216	15	0	1
T13	0	8	0	1
T15	2220	3	0	1
T20	1768	0	0	0
T22	4103	3	0	1
T23	1004	4	0	0
T24	2888	0	0	0
T37	0	3	0	1
T38	813	0	0	0
T49	0	3	0	1
T65	0	3	0	1
T66	0	3	0	1
T67	0	46	0	1
T68	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	4819	0	114
T5	1472	0	0	0
T12	2216	56	0	1
T14	0	0	0	1
T15	2220	18	0	1
T20	1768	0	0	0
T28	0	1	0	0
T37	1687	50	0	1
T38	813	0	0	0
T40	2191	0	0	0
T41	2404	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T65	0	34	0	1
T69	0	4	0	1
T70	0	11	0	1
T71	0	4	0	1
T72	0	3	0	1
T73	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	6683	0	100
T4	1892	0	0	0
T9	4739	3	0	1
T10	2482	0	0	0
T11	1867	0	0	0
T12	0	3	0	1
T13	0	17	0	1
T15	2220	19	0	1
T20	1768	0	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T37	0	3	0	1
T38	813	0	0	0
T39	0	0	0	1
T68	0	3	0	1
T69	0	4	0	0
T74	0	3	0	1
T75	0	4	0	1
T76	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	54065	0	108
T4	1892	0	0	0
T9	4739	60	0	1
T10	2482	0	0	0
T11	1867	0	0	0
T12	0	3	0	1
T13	0	65	0	1
T15	2220	3	0	1
T20	1768	0	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T37	0	36	0	1
T38	813	3	0	1
T40	0	3	0	1
T68	0	3	0	1
T70	0	0	0	1
T76	0	65	0	1
T77	0	4	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	1943	0	87
T3	1519	11	0	1
T4	1892	0	0	0
T9	4739	3	0	1
T10	2482	0	0	0
T11	1867	0	0	0
T13	0	3	0	1
T15	2220	52	0	1
T21	1893	4	0	1
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T30	0	1	0	0
T37	0	60	0	1
T40	0	47	0	1
T53	0	8	0	1
T70	0	0	0	1
T78	0	8	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	561111	0	320
T1	504975	1261	0	2
T2	1464	17	0	0
T3	1519	27	0	0
T4	1892	1081	0	0
T9	4739	253	0	0
T10	2482	179	0	0
T11	0	0	0	2
T16	0	0	0	2
T21	1893	178	0	0
T22	4103	60	0	0
T23	1004	28	0	0
T24	2888	16	0	0
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	2925	0	90
T4	1892	0	0	0
T9	4739	279	0	1
T10	2482	0	0	0
T11	1867	0	0	0
T12	0	3	0	1
T15	2220	15	0	1
T20	1768	0	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T37	0	3	0	1
T38	813	0	0	0
T40	0	15	0	1
T41	0	4	0	1
T43	0	1	0	0
T70	0	3	0	1
T73	0	0	0	1
T79	0	4	0	1
T80	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	128868	0	0
T4	1892	1106	0	0
T5	1472	822	0	0
T6	0	1130	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7237	0	0
T17	0	1074	0	0
T20	1768	0	0	0
T30	0	28	0	0
T31	0	26	0	0
T32	0	600	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	612	0	0
T64	0	1112	0	0