Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	250265488	11075573	0	0
boot_gen_cmd_rd_A	250265488	78998	0	0
boot_ins_cmd_rd_A	250265488	90476	0	0
ctrl_rd_A	250265488	78613	0	0
err_code_test_rd_A	250265488	89794	0	0
intr_enable_rd_A	250265488	86259	0	0
max_num_reqs_between_reseeds_rd_A	250265488	79922	0	0
regwen_rd_A	250265488	91123	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	11075573	0	0
T1	504975	205881	0	0
T2	1464	0	0	0
T3	1519	0	0	0
T4	1892	0	0	0
T9	4739	0	0	0
T10	2482	0	0	0
T21	1893	0	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T35	0	486452	0	0
T36	0	537284	0	0
T62	0	312716	0	0
T88	0	296565	0	0
T211	0	339533	0	0
T212	0	197893	0	0
T213	0	76784	0	0
T214	0	148817	0	0
T215	0	392035	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	78998	0	0
T213	217765	2204	0	0
T214	0	4076	0	0
T216	0	1561	0	0
T217	0	6983	0	0
T218	0	1995	0	0
T219	0	14170	0	0
T220	0	1184	0	0
T221	0	2954	0	0
T222	0	3322	0	0
T223	0	5771	0	0
T224	20907	0	0	0
T225	1924	0	0	0
T226	1122	0	0	0
T227	2356	0	0	0
T228	1731	0	0	0
T229	14154	0	0	0
T230	2636	0	0	0
T231	2965	0	0	0
T232	3298	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	90476	0	0
T213	217765	2742	0	0
T214	0	4971	0	0
T216	0	1525	0	0
T217	0	7970	0	0
T218	0	2138	0	0
T219	0	16699	0	0
T220	0	1638	0	0
T221	0	3152	0	0
T222	0	3907	0	0
T223	0	6555	0	0
T224	20907	0	0	0
T225	1924	0	0	0
T226	1122	0	0	0
T227	2356	0	0	0
T228	1731	0	0	0
T229	14154	0	0	0
T230	2636	0	0	0
T231	2965	0	0	0
T232	3298	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	78613	0	0
T7	1273	0	0	0
T33	1287	0	0	0
T84	643	0	0	0
T123	2078	0	0	0
T133	2975	0	0	0
T146	2399	0	0	0
T157	0	1	0	0
T181	2369	0	0	0
T213	0	2194	0	0
T214	0	4225	0	0
T216	0	1421	0	0
T224	0	9	0	0
T233	19055	3	0	0
T234	0	1	0	0
T235	0	2	0	0
T236	0	4	0	0
T237	0	2	0	0
T238	2613	0	0	0
T239	13005	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	89794	0	0
T213	217765	3018	0	0
T214	0	4840	0	0
T216	0	1693	0	0
T217	0	7639	0	0
T218	0	2166	0	0
T219	0	16351	0	0
T220	0	1486	0	0
T221	0	3115	0	0
T222	0	4051	0	0
T223	0	6883	0	0
T224	20907	0	0	0
T225	1924	0	0	0
T226	1122	0	0	0
T227	2356	0	0	0
T228	1731	0	0	0
T229	14154	0	0	0
T230	2636	0	0	0
T231	2965	0	0	0
T232	3298	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	86259	0	0
T13	3173	0	0	0
T16	21740	0	0	0
T30	764	0	0	0
T42	16458	95	0	0
T53	1499	0	0	0
T54	2710	0	0	0
T55	2385	0	0	0
T56	3417	0	0	0
T57	2086	0	0	0
T74	1003	0	0	0
T213	0	2535	0	0
T214	0	5117	0	0
T216	0	1606	0	0
T224	0	40	0	0
T233	0	55	0	0
T240	0	86	0	0
T241	0	63	0	0
T242	0	26	0	0
T243	0	60	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	79922	0	0
T213	217765	2296	0	0
T214	0	4353	0	0
T216	0	1471	0	0
T217	0	7211	0	0
T218	0	1989	0	0
T219	0	14395	0	0
T220	0	1252	0	0
T221	0	2760	0	0
T222	0	3285	0	0
T223	0	5539	0	0
T224	20907	0	0	0
T225	1924	0	0	0
T226	1122	0	0	0
T227	2356	0	0	0
T228	1731	0	0	0
T229	14154	0	0	0
T230	2636	0	0	0
T231	2965	0	0	0
T232	3298	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250265488	91123	0	0
T213	217765	2838	0	0
T214	0	4922	0	0
T216	0	1772	0	0
T217	0	8207	0	0
T218	0	2046	0	0
T219	0	15464	0	0
T220	0	1494	0	0
T221	0	3301	0	0
T222	0	4011	0	0
T223	0	6772	0	0
T224	20907	0	0	0
T225	1924	0	0	0
T226	1122	0	0	0
T227	2356	0	0	0
T228	1731	0	0	0
T229	14154	0	0	0
T230	2636	0	0	0
T231	2965	0	0	0
T232	3298	0	0	0